arm64: dts: rockchip: Add VPU121 support for RK3588

Enable Hantro G1 video decoder in RK3588's devicetree.

Tested with FFmpeg v4l2_request code taken from [1]
with MPEG2, H.264 and VP8 samples.

[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch

Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Tested-by: Hugh Cole-Baker <sigmaris@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240827181206.147617-3-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 595f129a2d8c3dd27bc53b1bcc48645c497a5c4e..14b8d869125588c9a0d98aace3331790ab6c3c51 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1122,6 +1122,27 @@
                };
        };
 
+       vpu121: video-codec@fdb50000 {
+               compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
+               reg = <0x0 0xfdb50000 0x0 0x800>;
+               interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "vdpu";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               clock-names = "aclk", "hclk";
+               iommus = <&vpu121_mmu>;
+               power-domains = <&power RK3588_PD_VDPU>;
+       };
+
+       vpu121_mmu: iommu@fdb50800 {
+               compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+               reg = <0x0 0xfdb50800 0x0 0x40>;
+               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+               clock-names = "aclk", "iface";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               power-domains = <&power RK3588_PD_VDPU>;
+               #iommu-cells = <0>;
+       };
+
        vepu121_0: video-codec@fdba0000 {
                compatible = "rockchip,rk3588-vepu121";
                reg = <0x0 0xfdba0000 0x0 0x800>;