drm/i915/dsi: Don't set/read the DSI C clock divider on GLK

GLK doesn't use the DSI C clock at all, no need to program
the divider for it. Bspec even says: "Do not program this field".

However looks like some firmware versions program this and
some do not. In order to avoid bogus fastset mismatches
we should also filter it out during readout.

v2: Clear all the DSI C clock bits during readout (Jani)
    Adjust platform checks for new style, and add
    has_dsic_clock() while at it.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250718112928.27669-1-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index d42b61e6f076421ce4ef1bcd33b11e7e0afaeafb..b52463fdec472c151ef4461ead1f62794b7dd32a 100644 (file)
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -262,6 +262,11 @@ void vlv_dsi_pll_disable(struct intel_encoder *encoder)
        vlv_cck_put(display->drm);
 }
 
+static bool has_dsic_clock(struct intel_display *display)
+{
+       return display->platform.broxton;
+}
+
 bool bxt_dsi_pll_is_enabled(struct intel_display *display)
 {
        bool enabled;
@@ -284,7 +289,7 @@ bool bxt_dsi_pll_is_enabled(struct intel_display *display)
         * causes a system hang.
         */
        val = intel_de_read(display, BXT_DSI_PLL_CTL);
-       if (display->platform.geminilake) {
+       if (!has_dsic_clock(display)) {
                if (!(val & BXT_DSIA_16X_MASK)) {
                        drm_dbg_kms(display->drm,
                                    "Invalid PLL divider (%08x)\n", val);
@@ -358,6 +363,8 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
        u32 pclk;
 
        config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);
+       if (!has_dsic_clock(display))
+               config->dsi_pll.ctrl &= ~BXT_DSIC_16X_MASK;
 
        pclk = bxt_dsi_pclk(encoder, config);
 
@@ -514,7 +521,9 @@ int bxt_dsi_pll_compute(struct intel_encoder *encoder,
         * Spec says both have to be programmed, even if one is not getting
         * used. Configure MIPI_CLOCK_CTL dividers in modeset
         */
-       config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
+       config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2;
+       if (has_dsic_clock(display))
+               config->dsi_pll.ctrl |= BXT_DSIC_16X_BY2;
 
        /* As per recommendation from hardware team,
         * Prog PVD ratio =1 if dsi ratio <= 50