drm/i915/dg1: Adjust the AUDIO power domain

DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
well. Adjusting the power domain accordingly to
POWER_DOMAIN_AUDIO_MMIO for audio detection and
POWER_DOMAIN_AUDIO_PLAYBACK for audio playback.

While doing this it requires to use POWER_DOMAIN_AUDIO_MMIO
power domain instead of POWER_DOMAIN_AUDIO in crtc power domain mask
and POWER_DOMAIN_AUDIO_PLAYBACK with intel_display_power_{get, put}
to enable/disable display audio codec power.

It will save the power in use cases when DP/HDMI connectors
configured with PIPE_A without any audio playback.

v1: Changes since RFC
- changed power domain names. [Imre]
- Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1
  power well and PW_3 power domains. [Imre]
- Fixed the order of powe wells , power domains and its
  registration. [Imre]

v2:
- Not allowe DC states when AUDIO_MMIO domain enabled. [Imre]

v3:
- Squashes the commits of series to avoid build failure.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
[Fix typo in commit message and in AUDIO_PLAYBACK domain name]
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729121858.16897-2-anshuman.gupta@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 5f4f316b3ab5ce48a57ced93d3b9e64bb8e86484..532237588511822c336c998a7181d794ff787b70 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -1001,7 +1001,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
        /* Catch potential impedance mismatches before they occur! */
        BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
 
-       ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+       ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
 
        if (dev_priv->audio_power_refcount++ == 0) {
                if (DISPLAY_VER(dev_priv) >= 9) {
@@ -1034,7 +1034,7 @@ static void i915_audio_component_put_power(struct device *kdev,
                if (IS_GEMINILAKE(dev_priv))
                        glk_force_audio_cdclk(dev_priv, false);
 
-       intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
+       intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
 }
 
 static void i915_audio_component_codec_wake_override(struct device *kdev,

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 39dfdadfde40080a75f5554c36934dd4ff2bb5ea..d8162951b78f8404fd2d2efdea4b06dd7b0fac4e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3414,7 +3414,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
        if (cpu_transcoder == TRANSCODER_EDP)
                return false;
 
-       if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
+       if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
                return false;
 
        return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0efea2a17e1020c545bda200fa11ab870de1feb6..3faedcb7ef423da1ecfda139e30b568ab1feb9bb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3931,7 +3931,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
        }
 
        if (HAS_DDI(dev_priv) && crtc_state->has_audio)
-               mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
+               mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
 
        if (crtc_state->shared_dpll)
                mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 02452237ad0b7741155881ad11dc4326402a0b69..5da293369f30b58a288d169b3bad3ccd605e473a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -107,8 +107,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
                return "PORT_OTHER";
        case POWER_DOMAIN_VGA:
                return "VGA";
-       case POWER_DOMAIN_AUDIO:
-               return "AUDIO";
+       case POWER_DOMAIN_AUDIO_MMIO:
+               return "AUDIO_MMIO";
+       case POWER_DOMAIN_AUDIO_PLAYBACK:
+               return "AUDIO_PLAYBACK";
        case POWER_DOMAIN_AUX_A:
                return "AUX_A";
        case POWER_DOMAIN_AUX_B:
@@ -2509,7 +2511,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
        BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
        BIT_ULL(POWER_DOMAIN_VGA) |                     \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |           \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |          \
        BIT_ULL(POWER_DOMAIN_AUX_B) |           \
        BIT_ULL(POWER_DOMAIN_AUX_C) |           \
        BIT_ULL(POWER_DOMAIN_GMBUS) |           \
@@ -2559,7 +2562,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
        BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
        BIT_ULL(POWER_DOMAIN_VGA) |                     \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |           \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |          \
        BIT_ULL(POWER_DOMAIN_AUX_B) |           \
        BIT_ULL(POWER_DOMAIN_AUX_C) |           \
        BIT_ULL(POWER_DOMAIN_AUX_D) |           \
@@ -2592,7 +2596,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
        BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
        BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_INIT))
 
 #define BDW_DISPLAY_POWER_DOMAINS (                    \
@@ -2608,7 +2613,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
        BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
        BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_INIT))
 
 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
@@ -2626,7 +2632,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
        BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
        BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_VGA) |                             \
        BIT_ULL(POWER_DOMAIN_INIT))
 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (         \
@@ -2661,7 +2668,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
        BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
        BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_VGA) |                             \
        BIT_ULL(POWER_DOMAIN_INIT))
 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (             \
@@ -2694,7 +2702,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
        BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
        BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_VGA) |                             \
        BIT_ULL(POWER_DOMAIN_INIT))
 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS (           \
@@ -2774,7 +2783,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_AUX_E_TBT) |               \
        BIT_ULL(POWER_DOMAIN_AUX_F_TBT) |               \
        BIT_ULL(POWER_DOMAIN_VGA) |                     \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_INIT))
        /*
         * - transcoder WD
@@ -2866,7 +2876,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_AUX_TBT5) |                \
        BIT_ULL(POWER_DOMAIN_AUX_TBT6) |                \
        BIT_ULL(POWER_DOMAIN_VGA) |                     \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_INIT))
 
 #define TGL_PW_2_POWER_DOMAINS (                       \
@@ -2936,7 +2947,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        RKL_PW_4_POWER_DOMAINS |                        \
        BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
        BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_VGA) |                     \
        BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) |      \
@@ -2973,6 +2985,35 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
        BIT_ULL(POWER_DOMAIN_INIT))
 
+/*
+ * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
+ */
+#define DG1_PW_3_POWER_DOMAINS (                       \
+       TGL_PW_4_POWER_DOMAINS |                        \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) |      \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) |      \
+       BIT_ULL(POWER_DOMAIN_AUX_USBC1) |               \
+       BIT_ULL(POWER_DOMAIN_AUX_USBC2) |               \
+       BIT_ULL(POWER_DOMAIN_VGA) |                     \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS (                       \
+       DG1_PW_3_POWER_DOMAINS |                        \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |     \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS (             \
+       DG1_PW_3_POWER_DOMAINS |                        \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
+       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
 /*
  * XE_LPD Power Domains
  *
@@ -3018,7 +3059,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
        XELPD_PW_B_POWER_DOMAINS |                      \
        XELPD_PW_C_POWER_DOMAINS |                      \
        XELPD_PW_D_POWER_DOMAINS |                      \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |                  \
        BIT_ULL(POWER_DOMAIN_VGA) |                     \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) |  \
@@ -3059,6 +3100,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 
 #define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS (           \
        XELPD_PW_2_POWER_DOMAINS |                      \
+       BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |              \
        BIT_ULL(POWER_DOMAIN_MODESET) |                 \
        BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
        BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
@@ -4445,6 +4487,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
        },
 };
 
+static const struct i915_power_well_desc dg1_power_wells[] = {
+       {
+               .name = "always-on",
+               .always_on = true,
+               .domains = POWER_DOMAIN_MASK,
+               .ops = &i9xx_always_on_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+       },
+       {
+               .name = "power well 1",
+               /* Handled by the DMC firmware */
+               .always_on = true,
+               .domains = 0,
+               .ops = &hsw_power_well_ops,
+               .id = SKL_DISP_PW_1,
+               {
+                       .hsw.regs = &hsw_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+                       .hsw.has_fuses = true,
+               },
+       },
+       {
+               .name = "DC off",
+               .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+               .ops = &gen9_dc_off_power_well_ops,
+               .id = SKL_DISP_DC_OFF,
+       },
+       {
+               .name = "power well 2",
+               .domains = DG1_PW_2_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = SKL_DISP_PW_2,
+               {
+                       .hsw.regs = &hsw_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+                       .hsw.has_fuses = true,
+               },
+       },
+       {
+               .name = "power well 3",
+               .domains = DG1_PW_3_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = ICL_DISP_PW_3,
+               {
+                       .hsw.regs = &hsw_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+                       .hsw.irq_pipe_mask = BIT(PIPE_B),
+                       .hsw.has_vga = true,
+                       .hsw.has_fuses = true,
+               },
+       },
+       {
+               .name = "DDI A IO",
+               .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_ddi_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+               }
+       },
+       {
+               .name = "DDI B IO",
+               .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_ddi_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+               }
+       },
+       {
+               .name = "DDI IO TC1",
+               .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_ddi_power_well_regs,
+                       .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+               },
+       },
+       {
+               .name = "DDI IO TC2",
+               .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_ddi_power_well_regs,
+                       .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+               },
+       },
+       {
+               .name = "AUX A",
+               .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+               .ops = &icl_aux_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_aux_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+               },
+       },
+       {
+               .name = "AUX B",
+               .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+               .ops = &icl_aux_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_aux_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+               },
+       },
+       {
+               .name = "AUX USBC1",
+               .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+               .ops = &icl_aux_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_aux_power_well_regs,
+                       .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+                       .hsw.is_tc_tbt = false,
+               },
+       },
+       {
+               .name = "AUX USBC2",
+               .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+               .ops = &icl_aux_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &icl_aux_power_well_regs,
+                       .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+                       .hsw.is_tc_tbt = false,
+               },
+       },
+       {
+               .name = "power well 4",
+               .domains = TGL_PW_4_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &hsw_power_well_regs,
+                       .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+                       .hsw.has_fuses = true,
+                       .hsw.irq_pipe_mask = BIT(PIPE_C),
+               }
+       },
+       {
+               .name = "power well 5",
+               .domains = TGL_PW_5_POWER_DOMAINS,
+               .ops = &hsw_power_well_ops,
+               .id = DISP_PW_ID_NONE,
+               {
+                       .hsw.regs = &hsw_power_well_regs,
+                       .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+                       .hsw.has_fuses = true,
+                       .hsw.irq_pipe_mask = BIT(PIPE_D),
+               },
+       },
+};
+
 static const struct i915_power_well_desc xelpd_power_wells[] = {
        {
                .name = "always-on",
@@ -4929,7 +5130,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
                err = 0;
        } else if (DISPLAY_VER(dev_priv) >= 13) {
                err = set_power_wells(power_domains, xelpd_power_wells);
-       } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
+       } else if (IS_DG1(dev_priv)) {
+               err = set_power_wells(power_domains, dg1_power_wells);
+       } else if (IS_ALDERLAKE_S(dev_priv)) {
                err = set_power_wells_mask(power_domains, tgl_power_wells,
                                           BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
        } else if (IS_ROCKETLAKE(dev_priv)) {

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index c79f7ca739d2c81a68908fb6e5c961932b7a133d..978531841fa3fe521da42f0f5f37b45d8fd28e22 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -76,7 +76,8 @@ enum intel_display_power_domain {
        POWER_DOMAIN_PORT_CRT,
        POWER_DOMAIN_PORT_OTHER,
        POWER_DOMAIN_VGA,
-       POWER_DOMAIN_AUDIO,
+       POWER_DOMAIN_AUDIO_MMIO,
+       POWER_DOMAIN_AUDIO_PLAYBACK,
        POWER_DOMAIN_AUX_A,
        POWER_DOMAIN_AUX_B,
        POWER_DOMAIN_AUX_C,