--- /dev/null
-#include "drmP.h"
-#include "drm.h"
-#include "drm_crtc.h"
-#include "drm_crtc_helper.h"
+ /*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp@keithp.com>
+ *
+ */
+
+ #include <linux/i2c.h>
+ #include <linux/slab.h>
-#include "drm_dp_helper.h"
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_crtc_helper.h>
+ #include "psb_drv.h"
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
++#include <drm/drm_dp_helper.h>
+
+ #define _wait_for(COND, MS, W) ({ \
+ unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
+ int ret__ = 0; \
+ while (! (COND)) { \
+ if (time_after(jiffies, timeout__)) { \
+ ret__ = -ETIMEDOUT; \
+ break; \
+ } \
+ if (W && !in_dbg_master()) msleep(W); \
+ } \
+ ret__; \
+ })
+
+ #define wait_for(COND, MS) _wait_for(COND, MS, 1)
+
+ #define DP_LINK_STATUS_SIZE 6
+ #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+
+ #define DP_LINK_CONFIGURATION_SIZE 9
+
+ #define CDV_FAST_LINK_TRAIN 1
+
+ struct cdv_intel_dp {
+ uint32_t output_reg;
+ uint32_t DP;
+ uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
+ bool has_audio;
+ int force_audio;
+ uint32_t color_range;
+ uint8_t link_bw;
+ uint8_t lane_count;
+ uint8_t dpcd[4];
+ struct psb_intel_encoder *encoder;
+ struct i2c_adapter adapter;
+ struct i2c_algo_dp_aux_data algo;
+ uint8_t train_set[4];
+ uint8_t link_status[DP_LINK_STATUS_SIZE];
+ int panel_power_up_delay;
+ int panel_power_down_delay;
+ int panel_power_cycle_delay;
+ int backlight_on_delay;
+ int backlight_off_delay;
+ struct drm_display_mode *panel_fixed_mode; /* for eDP */
+ bool panel_on;
+ };
+
+ struct ddi_regoff {
+ uint32_t PreEmph1;
+ uint32_t PreEmph2;
+ uint32_t VSwing1;
+ uint32_t VSwing2;
+ uint32_t VSwing3;
+ uint32_t VSwing4;
+ uint32_t VSwing5;
+ };
+
+ static struct ddi_regoff ddi_DP_train_table[] = {
+ {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
+ .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
+ .VSwing5 = 0x8158,},
+ {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
+ .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
+ .VSwing5 = 0x8258,},
+ };
+
+ static uint32_t dp_vswing_premph_table[] = {
+ 0x55338954, 0x4000,
+ 0x554d8954, 0x2000,
+ 0x55668954, 0,
+ 0x559ac0d4, 0x6000,
+ };
+ /**
+ * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
+ * @intel_dp: DP struct
+ *
+ * If a CPU or PCH DP output is attached to an eDP panel, this function
+ * will return true, and false otherwise.
+ */
+ static bool is_edp(struct psb_intel_encoder *encoder)
+ {
+ return encoder->type == INTEL_OUTPUT_EDP;
+ }
+
+
+ static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
+ static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
+ static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
+
+ static int
+ cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_lane_count = 4;
+
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+ max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
+ switch (max_lane_count) {
+ case 1: case 2: case 4:
+ break;
+ default:
+ max_lane_count = 4;
+ }
+ }
+ return max_lane_count;
+ }
+
+ static int
+ cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
+
+ switch (max_link_bw) {
+ case DP_LINK_BW_1_62:
+ case DP_LINK_BW_2_7:
+ break;
+ default:
+ max_link_bw = DP_LINK_BW_1_62;
+ break;
+ }
+ return max_link_bw;
+ }
+
+ static int
+ cdv_intel_dp_link_clock(uint8_t link_bw)
+ {
+ if (link_bw == DP_LINK_BW_2_7)
+ return 270000;
+ else
+ return 162000;
+ }
+
+ static int
+ cdv_intel_dp_link_required(int pixel_clock, int bpp)
+ {
+ return (pixel_clock * bpp + 7) / 8;
+ }
+
+ static int
+ cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
+ {
+ return (max_link_clock * max_lanes * 19) / 20;
+ }
+
+ static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ u32 pp;
+
+ if (intel_dp->panel_on) {
+ DRM_DEBUG_KMS("Skip VDD on because of panel on\n");
+ return;
+ }
+ DRM_DEBUG_KMS("\n");
+
+ pp = REG_READ(PP_CONTROL);
+
+ pp |= EDP_FORCE_VDD;
+ REG_WRITE(PP_CONTROL, pp);
+ REG_READ(PP_CONTROL);
+ msleep(intel_dp->panel_power_up_delay);
+ }
+
+ static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ u32 pp;
+
+ DRM_DEBUG_KMS("\n");
+ pp = REG_READ(PP_CONTROL);
+
+ pp &= ~EDP_FORCE_VDD;
+ REG_WRITE(PP_CONTROL, pp);
+ REG_READ(PP_CONTROL);
+
+ }
+
+ /* Returns true if the panel was already on when called */
+ static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
+
+ if (intel_dp->panel_on)
+ return true;
+
+ DRM_DEBUG_KMS("\n");
+ pp = REG_READ(PP_CONTROL);
+ pp &= ~PANEL_UNLOCK_MASK;
+
+ pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);
+ REG_WRITE(PP_CONTROL, pp);
+ REG_READ(PP_CONTROL);
+
+ if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
+ DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
+ intel_dp->panel_on = false;
+ } else
+ intel_dp->panel_on = true;
+ msleep(intel_dp->panel_power_up_delay);
+
+ return false;
+ }
+
+ static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ u32 pp, idle_off_mask = PP_ON ;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+
+ DRM_DEBUG_KMS("\n");
+
+ pp = REG_READ(PP_CONTROL);
+
+ if ((pp & POWER_TARGET_ON) == 0)
+ return;
+
+ intel_dp->panel_on = false;
+ pp &= ~PANEL_UNLOCK_MASK;
+ /* ILK workaround: disable reset around power sequence */
+
+ pp &= ~POWER_TARGET_ON;
+ pp &= ~EDP_FORCE_VDD;
+ pp &= ~EDP_BLC_ENABLE;
+ REG_WRITE(PP_CONTROL, pp);
+ REG_READ(PP_CONTROL);
+ DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));
+
+ if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
+ DRM_DEBUG_KMS("Error in turning off Panel\n");
+ }
+
+ msleep(intel_dp->panel_power_cycle_delay);
+ DRM_DEBUG_KMS("Over\n");
+ }
+
+ static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ u32 pp;
+
+ DRM_DEBUG_KMS("\n");
+ /*
+ * If we enable the backlight right away following a panel power
+ * on, we may see slight flicker as the panel syncs with the eDP
+ * link. So delay a bit to make sure the image is solid before
+ * allowing it to appear.
+ */
+ msleep(300);
+ pp = REG_READ(PP_CONTROL);
+
+ pp |= EDP_BLC_ENABLE;
+ REG_WRITE(PP_CONTROL, pp);
+ gma_backlight_enable(dev);
+ }
+
+ static void cdv_intel_edp_backlight_off (struct psb_intel_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ u32 pp;
+
+ DRM_DEBUG_KMS("\n");
+ gma_backlight_disable(dev);
+ msleep(10);
+ pp = REG_READ(PP_CONTROL);
+
+ pp &= ~EDP_BLC_ENABLE;
+ REG_WRITE(PP_CONTROL, pp);
+ msleep(intel_dp->backlight_off_delay);
+ }
+
+ static int
+ cdv_intel_dp_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+ {
+ struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
+ int max_lanes = cdv_intel_dp_max_lane_count(encoder);
+ struct drm_psb_private *dev_priv = connector->dev->dev_private;
+
+ if (is_edp(encoder) && intel_dp->panel_fixed_mode) {
+ if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
+ return MODE_PANEL;
+ if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
+ return MODE_PANEL;
+ }
+
+ /* only refuse the mode on non eDP since we have seen some weird eDP panels
+ which are outside spec tolerances but somehow work by magic */
+ if (!is_edp(encoder) &&
+ (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
+ > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
+ return MODE_CLOCK_HIGH;
+
+ if (is_edp(encoder)) {
+ if (cdv_intel_dp_link_required(mode->clock, 24)
+ > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))
+ return MODE_CLOCK_HIGH;
+
+ }
+ if (mode->clock < 10000)
+ return MODE_CLOCK_LOW;
+
+ return MODE_OK;
+ }
+
+ static uint32_t
+ pack_aux(uint8_t *src, int src_bytes)
+ {
+ int i;
+ uint32_t v = 0;
+
+ if (src_bytes > 4)
+ src_bytes = 4;
+ for (i = 0; i < src_bytes; i++)
+ v |= ((uint32_t) src[i]) << ((3-i) * 8);
+ return v;
+ }
+
+ static void
+ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+ {
+ int i;
+ if (dst_bytes > 4)
+ dst_bytes = 4;
+ for (i = 0; i < dst_bytes; i++)
+ dst[i] = src >> ((3-i) * 8);
+ }
+
+ static int
+ cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
+ uint8_t *send, int send_bytes,
+ uint8_t *recv, int recv_size)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ uint32_t output_reg = intel_dp->output_reg;
+ struct drm_device *dev = encoder->base.dev;
+ uint32_t ch_ctl = output_reg + 0x10;
+ uint32_t ch_data = ch_ctl + 4;
+ int i;
+ int recv_bytes;
+ uint32_t status;
+ uint32_t aux_clock_divider;
+ int try, precharge;
+
+ /* The clock divider is based off the hrawclk,
+ * and would like to run at 2MHz. So, take the
+ * hrawclk value and divide by 2 and use that
+ * On CDV platform it uses 200MHz as hrawclk.
+ *
+ */
+ aux_clock_divider = 200 / 2;
+
+ precharge = 4;
+ if (is_edp(encoder))
+ precharge = 10;
+
+ if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
+ DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
+ REG_READ(ch_ctl));
+ return -EBUSY;
+ }
+
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ /* Load the send data into the aux channel data registers */
+ for (i = 0; i < send_bytes; i += 4)
+ REG_WRITE(ch_data + i,
+ pack_aux(send + i, send_bytes - i));
+
+ /* Send the command and wait for it to complete */
+ REG_WRITE(ch_ctl,
+ DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_TIME_OUT_400us |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+ (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
+ for (;;) {
+ status = REG_READ(ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ udelay(100);
+ }
+
+ /* Clear done status and any errors */
+ REG_WRITE(ch_ctl,
+ status |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
+ if (status & DP_AUX_CH_CTL_DONE)
+ break;
+ }
+
+ if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+ DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
+ return -EBUSY;
+ }
+
+ /* Check for timeout or receive error.
+ * Timeouts occur when the sink is not connected
+ */
+ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
+ return -EIO;
+ }
+
+ /* Timeouts occur when the device isn't connected, so they're
+ * "normal" -- don't fill the kernel log with these */
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
+ return -ETIMEDOUT;
+ }
+
+ /* Unload any bytes sent back from the other side */
+ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+ DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+ if (recv_bytes > recv_size)
+ recv_bytes = recv_size;
+
+ for (i = 0; i < recv_bytes; i += 4)
+ unpack_aux(REG_READ(ch_data + i),
+ recv + i, recv_bytes - i);
+
+ return recv_bytes;
+ }
+
+ /* Write data to the aux channel in native mode */
+ static int
+ cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
+ uint16_t address, uint8_t *send, int send_bytes)
+ {
+ int ret;
+ uint8_t msg[20];
+ int msg_bytes;
+ uint8_t ack;
+
+ if (send_bytes > 16)
+ return -1;
+ msg[0] = AUX_NATIVE_WRITE << 4;
+ msg[1] = address >> 8;
+ msg[2] = address & 0xff;
+ msg[3] = send_bytes - 1;
+ memcpy(&msg[4], send, send_bytes);
+ msg_bytes = send_bytes + 4;
+ for (;;) {
+ ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
+ if (ret < 0)
+ return ret;
+ if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+ break;
+ else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+ udelay(100);
+ else
+ return -EIO;
+ }
+ return send_bytes;
+ }
+
+ /* Write a single byte to the aux channel in native mode */
+ static int
+ cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
+ uint16_t address, uint8_t byte)
+ {
+ return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
+ }
+
+ /* read bytes from a native aux channel */
+ static int
+ cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
+ uint16_t address, uint8_t *recv, int recv_bytes)
+ {
+ uint8_t msg[4];
+ int msg_bytes;
+ uint8_t reply[20];
+ int reply_bytes;
+ uint8_t ack;
+ int ret;
+
+ msg[0] = AUX_NATIVE_READ << 4;
+ msg[1] = address >> 8;
+ msg[2] = address & 0xff;
+ msg[3] = recv_bytes - 1;
+
+ msg_bytes = 4;
+ reply_bytes = recv_bytes + 1;
+
+ for (;;) {
+ ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
+ reply, reply_bytes);
+ if (ret == 0)
+ return -EPROTO;
+ if (ret < 0)
+ return ret;
+ ack = reply[0];
+ if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
+ memcpy(recv, reply + 1, ret - 1);
+ return ret - 1;
+ }
+ else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+ udelay(100);
+ else
+ return -EIO;
+ }
+ }
+
+ static int
+ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
+ uint8_t write_byte, uint8_t *read_byte)
+ {
+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+ struct cdv_intel_dp *intel_dp = container_of(adapter,
+ struct cdv_intel_dp,
+ adapter);
+ struct psb_intel_encoder *encoder = intel_dp->encoder;
+ uint16_t address = algo_data->address;
+ uint8_t msg[5];
+ uint8_t reply[2];
+ unsigned retry;
+ int msg_bytes;
+ int reply_bytes;
+ int ret;
+
+ /* Set up the command byte */
+ if (mode & MODE_I2C_READ)
+ msg[0] = AUX_I2C_READ << 4;
+ else
+ msg[0] = AUX_I2C_WRITE << 4;
+
+ if (!(mode & MODE_I2C_STOP))
+ msg[0] |= AUX_I2C_MOT << 4;
+
+ msg[1] = address >> 8;
+ msg[2] = address;
+
+ switch (mode) {
+ case MODE_I2C_WRITE:
+ msg[3] = 0;
+ msg[4] = write_byte;
+ msg_bytes = 5;
+ reply_bytes = 1;
+ break;
+ case MODE_I2C_READ:
+ msg[3] = 0;
+ msg_bytes = 4;
+ reply_bytes = 2;
+ break;
+ default:
+ msg_bytes = 3;
+ reply_bytes = 1;
+ break;
+ }
+
+ for (retry = 0; retry < 5; retry++) {
+ ret = cdv_intel_dp_aux_ch(encoder,
+ msg, msg_bytes,
+ reply, reply_bytes);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
+ return ret;
+ }
+
+ switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
+ case AUX_NATIVE_REPLY_ACK:
+ /* I2C-over-AUX Reply field is only valid
+ * when paired with AUX ACK.
+ */
+ break;
+ case AUX_NATIVE_REPLY_NACK:
+ DRM_DEBUG_KMS("aux_ch native nack\n");
+ return -EREMOTEIO;
+ case AUX_NATIVE_REPLY_DEFER:
+ udelay(100);
+ continue;
+ default:
+ DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
+ reply[0]);
+ return -EREMOTEIO;
+ }
+
+ switch (reply[0] & AUX_I2C_REPLY_MASK) {
+ case AUX_I2C_REPLY_ACK:
+ if (mode == MODE_I2C_READ) {
+ *read_byte = reply[1];
+ }
+ return reply_bytes - 1;
+ case AUX_I2C_REPLY_NACK:
+ DRM_DEBUG_KMS("aux_i2c nack\n");
+ return -EREMOTEIO;
+ case AUX_I2C_REPLY_DEFER:
+ DRM_DEBUG_KMS("aux_i2c defer\n");
+ udelay(100);
+ break;
+ default:
+ DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
+ return -EREMOTEIO;
+ }
+ }
+
+ DRM_ERROR("too many retries, giving up\n");
+ return -EREMOTEIO;
+ }
+
+ static int
+ cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret;
+
+ DRM_DEBUG_KMS("i2c_init %s\n", name);
+
+ intel_dp->algo.running = false;
+ intel_dp->algo.address = 0;
+ intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
+
+ memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
+ intel_dp->adapter.owner = THIS_MODULE;
+ intel_dp->adapter.class = I2C_CLASS_DDC;
+ strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
+ intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
+ intel_dp->adapter.algo_data = &intel_dp->algo;
+ intel_dp->adapter.dev.parent = &connector->base.kdev;
+
+ if (is_edp(encoder))
+ cdv_intel_edp_panel_vdd_on(encoder);
+ ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
+ if (is_edp(encoder))
+ cdv_intel_edp_panel_vdd_off(encoder);
+
+ return ret;
+ }
+
+ void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
+ struct drm_display_mode *adjusted_mode)
+ {
+ adjusted_mode->hdisplay = fixed_mode->hdisplay;
+ adjusted_mode->hsync_start = fixed_mode->hsync_start;
+ adjusted_mode->hsync_end = fixed_mode->hsync_end;
+ adjusted_mode->htotal = fixed_mode->htotal;
+
+ adjusted_mode->vdisplay = fixed_mode->vdisplay;
+ adjusted_mode->vsync_start = fixed_mode->vsync_start;
+ adjusted_mode->vsync_end = fixed_mode->vsync_end;
+ adjusted_mode->vtotal = fixed_mode->vtotal;
+
+ adjusted_mode->clock = fixed_mode->clock;
+
+ drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
+ }
+
+ static bool
+ cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+ {
+ struct drm_psb_private *dev_priv = encoder->dev->dev_private;
+ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ int lane_count, clock;
+ int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
+ int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
+ static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+ int refclock = mode->clock;
+ int bpp = 24;
+
+ if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {
+ cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
+ refclock = intel_dp->panel_fixed_mode->clock;
+ bpp = dev_priv->edp.bpp;
+ }
+
+ for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
+ for (clock = max_clock; clock >= 0; clock--) {
+ int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
+
+ if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) {
+ intel_dp->link_bw = bws[clock];
+ intel_dp->lane_count = lane_count;
+ adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
+ DRM_DEBUG_KMS("Display port link bw %02x lane "
+ "count %d clock %d\n",
+ intel_dp->link_bw, intel_dp->lane_count,
+ adjusted_mode->clock);
+ return true;
+ }
+ }
+ }
+ if (is_edp(intel_encoder)) {
+ /* okay we failed just pick the highest */
+ intel_dp->lane_count = max_lane_count;
+ intel_dp->link_bw = bws[max_clock];
+ adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
+ DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
+ "count %d clock %d\n",
+ intel_dp->link_bw, intel_dp->lane_count,
+ adjusted_mode->clock);
+
+ return true;
+ }
+ return false;
+ }
+
+ struct cdv_intel_dp_m_n {
+ uint32_t tu;
+ uint32_t gmch_m;
+ uint32_t gmch_n;
+ uint32_t link_m;
+ uint32_t link_n;
+ };
+
+ static void
+ cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den)
+ {
+ /*
+ while (*num > 0xffffff || *den > 0xffffff) {
+ *num >>= 1;
+ *den >>= 1;
+ }*/
+ uint64_t value, m;
+ m = *num;
+ value = m * (0x800000);
+ m = do_div(value, *den);
+ *num = value;
+ *den = 0x800000;
+ }
+
+ static void
+ cdv_intel_dp_compute_m_n(int bpp,
+ int nlanes,
+ int pixel_clock,
+ int link_clock,
+ struct cdv_intel_dp_m_n *m_n)
+ {
+ m_n->tu = 64;
+ m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
+ m_n->gmch_n = link_clock * nlanes;
+ cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
+ m_n->link_m = pixel_clock;
+ m_n->link_n = link_clock;
+ cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
+ }
+
+ void
+ cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_encoder *encoder;
+ struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
+ int lane_count = 4, bpp = 24;
+ struct cdv_intel_dp_m_n m_n;
+ int pipe = intel_crtc->pipe;
+
+ /*
+ * Find the lane count in the intel_encoder private
+ */
+ list_for_each_entry(encoder, &mode_config->encoder_list, head) {
+ struct psb_intel_encoder *intel_encoder;
+ struct cdv_intel_dp *intel_dp;
+
+ if (encoder->crtc != crtc)
+ continue;
+
+ intel_encoder = to_psb_intel_encoder(encoder);
+ intel_dp = intel_encoder->dev_priv;
+ if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ lane_count = intel_dp->lane_count;
+ break;
+ } else if (is_edp(intel_encoder)) {
+ lane_count = intel_dp->lane_count;
+ bpp = dev_priv->edp.bpp;
+ break;
+ }
+ }
+
+ /*
+ * Compute the GMCH and Link ratios. The '3' here is
+ * the number of bytes_per_pixel post-LUT, which we always
+ * set up for 8-bits of R/G/B, or 3 bytes total.
+ */
+ cdv_intel_dp_compute_m_n(bpp, lane_count,
+ mode->clock, adjusted_mode->clock, &m_n);
+
+ {
+ REG_WRITE(PIPE_GMCH_DATA_M(pipe),
+ ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+ m_n.gmch_m);
+ REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
+ REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
+ REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
+ }
+ }
+
+ static void
+ cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+ {
+ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+ struct drm_crtc *crtc = encoder->crtc;
+ struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct drm_device *dev = encoder->dev;
+
+ intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+ intel_dp->DP |= intel_dp->color_range;
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ intel_dp->DP |= DP_SYNC_HS_HIGH;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ intel_dp->DP |= DP_SYNC_VS_HIGH;
+
+ intel_dp->DP |= DP_LINK_TRAIN_OFF;
+
+ switch (intel_dp->lane_count) {
+ case 1:
+ intel_dp->DP |= DP_PORT_WIDTH_1;
+ break;
+ case 2:
+ intel_dp->DP |= DP_PORT_WIDTH_2;
+ break;
+ case 4:
+ intel_dp->DP |= DP_PORT_WIDTH_4;
+ break;
+ }
+ if (intel_dp->has_audio)
+ intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
+
+ memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
+ intel_dp->link_configuration[0] = intel_dp->link_bw;
+ intel_dp->link_configuration[1] = intel_dp->lane_count;
+
+ /*
+ * Check for DPCD version > 1.1 and enhanced framing support
+ */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+ (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
+ intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ intel_dp->DP |= DP_ENHANCED_FRAMING;
+ }
+
+ /* CPT DP's pipe select is decided in TRANS_DP_CTL */
+ if (intel_crtc->pipe == 1)
+ intel_dp->DP |= DP_PIPEB_SELECT;
+
+ REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
+ DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
+ if (is_edp(intel_encoder)) {
+ uint32_t pfit_control;
+ cdv_intel_edp_panel_on(intel_encoder);
+
+ if (mode->hdisplay != adjusted_mode->hdisplay ||
+ mode->vdisplay != adjusted_mode->vdisplay)
+ pfit_control = PFIT_ENABLE;
+ else
+ pfit_control = 0;
+
+ pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT;
+
+ REG_WRITE(PFIT_CONTROL, pfit_control);
+ }
+ }
+
+
+ /* If the sink supports it, try to set the power state appropriately */
+ static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret, i;
+
+ /* Should have a valid DPCD by this point */
+ if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
+ return;
+
+ if (mode != DRM_MODE_DPMS_ON) {
+ ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
+ DP_SET_POWER_D3);
+ if (ret != 1)
+ DRM_DEBUG_DRIVER("failed to write sink power state\n");
+ } else {
+ /*
+ * When turning on, we need to retry for 1ms to give the sink
+ * time to wake up.
+ */
+ for (i = 0; i < 3; i++) {
+ ret = cdv_intel_dp_aux_native_write_1(encoder,
+ DP_SET_POWER,
+ DP_SET_POWER_D0);
+ if (ret == 1)
+ break;
+ udelay(1000);
+ }
+ }
+ }
+
+ static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
+ {
+ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+ int edp = is_edp(intel_encoder);
+
+ if (edp) {
+ cdv_intel_edp_backlight_off(intel_encoder);
+ cdv_intel_edp_panel_off(intel_encoder);
+ cdv_intel_edp_panel_vdd_on(intel_encoder);
+ }
+ /* Wake up the sink first */
+ cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
+ cdv_intel_dp_link_down(intel_encoder);
+ if (edp)
+ cdv_intel_edp_panel_vdd_off(intel_encoder);
+ }
+
+ static void cdv_intel_dp_commit(struct drm_encoder *encoder)
+ {
+ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+ int edp = is_edp(intel_encoder);
+
+ if (edp)
+ cdv_intel_edp_panel_on(intel_encoder);
+ cdv_intel_dp_start_link_train(intel_encoder);
+ cdv_intel_dp_complete_link_train(intel_encoder);
+ if (edp)
+ cdv_intel_edp_backlight_on(intel_encoder);
+ }
+
+ static void
+ cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
+ {
+ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct drm_device *dev = encoder->dev;
+ uint32_t dp_reg = REG_READ(intel_dp->output_reg);
+ int edp = is_edp(intel_encoder);
+
+ if (mode != DRM_MODE_DPMS_ON) {
+ if (edp) {
+ cdv_intel_edp_backlight_off(intel_encoder);
+ cdv_intel_edp_panel_vdd_on(intel_encoder);
+ }
+ cdv_intel_dp_sink_dpms(intel_encoder, mode);
+ cdv_intel_dp_link_down(intel_encoder);
+ if (edp) {
+ cdv_intel_edp_panel_vdd_off(intel_encoder);
+ cdv_intel_edp_panel_off(intel_encoder);
+ }
+ } else {
+ if (edp)
+ cdv_intel_edp_panel_on(intel_encoder);
+ cdv_intel_dp_sink_dpms(intel_encoder, mode);
+ if (!(dp_reg & DP_PORT_EN)) {
+ cdv_intel_dp_start_link_train(intel_encoder);
+ cdv_intel_dp_complete_link_train(intel_encoder);
+ }
+ if (edp)
+ cdv_intel_edp_backlight_on(intel_encoder);
+ }
+ }
+
+ /*
+ * Native read with retry for link status and receiver capability reads for
+ * cases where the sink may still be asleep.
+ */
+ static bool
+ cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
+ uint8_t *recv, int recv_bytes)
+ {
+ int ret, i;
+
+ /*
+ * Sinks are *supposed* to come up within 1ms from an off state,
+ * but we're also supposed to retry 3 times per the spec.
+ */
+ for (i = 0; i < 3; i++) {
+ ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
+ recv_bytes);
+ if (ret == recv_bytes)
+ return true;
+ udelay(1000);
+ }
+
+ return false;
+ }
+
+ /*
+ * Fetch AUX CH registers 0x202 - 0x207 which contain
+ * link status information
+ */
+ static bool
+ cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ return cdv_intel_dp_aux_native_read_retry(encoder,
+ DP_LANE0_1_STATUS,
+ intel_dp->link_status,
+ DP_LINK_STATUS_SIZE);
+ }
+
+ static uint8_t
+ cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
+ int r)
+ {
+ return link_status[r - DP_LANE0_1_STATUS];
+ }
+
+ static uint8_t
+ cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+ {
+ int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+ int s = ((lane & 1) ?
+ DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
+ DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
+ uint8_t l = cdv_intel_dp_link_status(link_status, i);
+
+ return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
+ }
+
+ static uint8_t
+ cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+ {
+ int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+ int s = ((lane & 1) ?
+ DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
+ DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
+ uint8_t l = cdv_intel_dp_link_status(link_status, i);
+
+ return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
+ }
+
+
+ #if 0
+ static char *voltage_names[] = {
+ "0.4V", "0.6V", "0.8V", "1.2V"
+ };
+ static char *pre_emph_names[] = {
+ "0dB", "3.5dB", "6dB", "9.5dB"
+ };
+ static char *link_train_names[] = {
+ "pattern 1", "pattern 2", "idle", "off"
+ };
+ #endif
+
+ #define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
+ /*
+ static uint8_t
+ cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
+ {
+ switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ return DP_TRAIN_PRE_EMPHASIS_6;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ return DP_TRAIN_PRE_EMPHASIS_6;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ return DP_TRAIN_PRE_EMPHASIS_3_5;
+ case DP_TRAIN_VOLTAGE_SWING_1200:
+ default:
+ return DP_TRAIN_PRE_EMPHASIS_0;
+ }
+ }
+ */
+ static void
+ cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ uint8_t v = 0;
+ uint8_t p = 0;
+ int lane;
+
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
+ uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
+
+ if (this_v > v)
+ v = this_v;
+ if (this_p > p)
+ p = this_p;
+ }
+
+ if (v >= CDV_DP_VOLTAGE_MAX)
+ v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
+
+ if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
+ p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (lane = 0; lane < 4; lane++)
+ intel_dp->train_set[lane] = v | p;
+ }
+
+
+ static uint8_t
+ cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+ {
+ int i = DP_LANE0_1_STATUS + (lane >> 1);
+ int s = (lane & 1) * 4;
+ uint8_t l = cdv_intel_dp_link_status(link_status, i);
+
+ return (l >> s) & 0xf;
+ }
+
+ /* Check for clock recovery is done on all channels */
+ static bool
+ cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
+ {
+ int lane;
+ uint8_t lane_status;
+
+ for (lane = 0; lane < lane_count; lane++) {
+ lane_status = cdv_intel_get_lane_status(link_status, lane);
+ if ((lane_status & DP_LANE_CR_DONE) == 0)
+ return false;
+ }
+ return true;
+ }
+
+ /* Check to see if channel eq is done on all channels */
+ #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
+ DP_LANE_CHANNEL_EQ_DONE|\
+ DP_LANE_SYMBOL_LOCKED)
+ static bool
+ cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ uint8_t lane_align;
+ uint8_t lane_status;
+ int lane;
+
+ lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
+ DP_LANE_ALIGN_STATUS_UPDATED);
+ if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
+ return false;
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
+ if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
+ return false;
+ }
+ return true;
+ }
+
+ static bool
+ cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
+ uint32_t dp_reg_value,
+ uint8_t dp_train_pat)
+ {
+
+ struct drm_device *dev = encoder->base.dev;
+ int ret;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+
+ REG_WRITE(intel_dp->output_reg, dp_reg_value);
+ REG_READ(intel_dp->output_reg);
+
+ ret = cdv_intel_dp_aux_native_write_1(encoder,
+ DP_TRAINING_PATTERN_SET,
+ dp_train_pat);
+
+ if (ret != 1) {
+ DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
+ dp_train_pat);
+ return false;
+ }
+
+ return true;
+ }
+
+
+ static bool
+ cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
+ uint8_t dp_train_pat)
+ {
+
+ int ret;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+
+ ret = cdv_intel_dp_aux_native_write(encoder,
+ DP_TRAINING_LANE0_SET,
+ intel_dp->train_set,
+ intel_dp->lane_count);
+
+ if (ret != intel_dp->lane_count) {
+ DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
+ intel_dp->train_set[0], intel_dp->lane_count);
+ return false;
+ }
+ return true;
+ }
+
+ static void
+ cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ struct ddi_regoff *ddi_reg;
+ int vswing, premph, index;
+
+ if (intel_dp->output_reg == DP_B)
+ ddi_reg = &ddi_DP_train_table[0];
+ else
+ ddi_reg = &ddi_DP_train_table[1];
+
+ vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
+ premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+ if (vswing + premph > 3)
+ return;
+ #ifdef CDV_FAST_LINK_TRAIN
+ return;
+ #endif
+ DRM_DEBUG_KMS("Test2\n");
+ //return ;
+ cdv_sb_reset(dev);
+ /* ;Swing voltage programming
+ ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
+ cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
+
+ /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
+ cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
+
+ /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
+ * The VSwing_PreEmph table is also considered based on the vswing/premp
+ */
+ index = (vswing + premph) * 2;
+ if (premph == 1 && vswing == 1) {
+ cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
+ } else
+ cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
+
+ /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
+ if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
+ cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
+ else
+ cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
+
+ /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
+ /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
+
+ /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
+ cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
+
+ /* ;Pre emphasis programming
+ * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
+ */
+ cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
+
+ /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
+ index = 2 * premph + 1;
+ cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
+ return;
+ }
+
+
+ /* Enable corresponding port and start training pattern 1 */
+ static void
+ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int i;
+ uint8_t voltage;
+ bool clock_recovery = false;
+ int tries;
+ u32 reg;
+ uint32_t DP = intel_dp->DP;
+
+ DP |= DP_PORT_EN;
+ DP &= ~DP_LINK_TRAIN_MASK;
+
+ reg = DP;
+ reg |= DP_LINK_TRAIN_PAT_1;
+ /* Enable output, wait for it to become active */
+ REG_WRITE(intel_dp->output_reg, reg);
+ REG_READ(intel_dp->output_reg);
+ psb_intel_wait_for_vblank(dev);
+
+ DRM_DEBUG_KMS("Link config\n");
+ /* Write the link configuration data */
+ cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
+ intel_dp->link_configuration,
+ 2);
+
+ memset(intel_dp->train_set, 0, 4);
+ voltage = 0;
+ tries = 0;
+ clock_recovery = false;
+
+ DRM_DEBUG_KMS("Start train\n");
+ reg = DP | DP_LINK_TRAIN_PAT_1;
+
+
+ for (;;) {
+ /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
+ DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
+ intel_dp->train_set[0],
+ intel_dp->link_configuration[0],
+ intel_dp->link_configuration[1]);
+
+ if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
+ DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
+ }
+ cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
+ /* Set training pattern 1 */
+
+ cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
+
+ udelay(200);
+ if (!cdv_intel_dp_get_link_status(encoder))
+ break;
+
+ DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
+ intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
+ intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
+
+ if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+ DRM_DEBUG_KMS("PT1 train is done\n");
+ clock_recovery = true;
+ break;
+ }
+
+ /* Check to see if we've tried the max voltage */
+ for (i = 0; i < intel_dp->lane_count; i++)
+ if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+ break;
+ if (i == intel_dp->lane_count)
+ break;
+
+ /* Check to see if we've tried the same voltage 5 times */
+ if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+ ++tries;
+ if (tries == 5)
+ break;
+ } else
+ tries = 0;
+ voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+
+ /* Compute new intel_dp->train_set as requested by target */
+ cdv_intel_get_adjust_train(encoder);
+
+ }
+
+ if (!clock_recovery) {
+ DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
+ }
+
+ intel_dp->DP = DP;
+ }
+
+ static void
+ cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ bool channel_eq = false;
+ int tries, cr_tries;
+ u32 reg;
+ uint32_t DP = intel_dp->DP;
+
+ /* channel equalization */
+ tries = 0;
+ cr_tries = 0;
+ channel_eq = false;
+
+ DRM_DEBUG_KMS("\n");
+ reg = DP | DP_LINK_TRAIN_PAT_2;
+
+ for (;;) {
+
+ DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
+ intel_dp->train_set[0],
+ intel_dp->link_configuration[0],
+ intel_dp->link_configuration[1]);
+ /* channel eq pattern */
+
+ if (!cdv_intel_dp_set_link_train(encoder, reg,
+ DP_TRAINING_PATTERN_2)) {
+ DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
+ }
+ /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
+
+ if (cr_tries > 5) {
+ DRM_ERROR("failed to train DP, aborting\n");
+ cdv_intel_dp_link_down(encoder);
+ break;
+ }
+
+ cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
+
+ cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
+
+ udelay(1000);
+ if (!cdv_intel_dp_get_link_status(encoder))
+ break;
+
+ DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
+ intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
+ intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
+
+ /* Make sure clock is still ok */
+ if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+ cdv_intel_dp_start_link_train(encoder);
+ cr_tries++;
+ continue;
+ }
+
+ if (cdv_intel_channel_eq_ok(encoder)) {
+ DRM_DEBUG_KMS("PT2 train is done\n");
+ channel_eq = true;
+ break;
+ }
+
+ /* Try 5 times, then try clock recovery if that fails */
+ if (tries > 5) {
+ cdv_intel_dp_link_down(encoder);
+ cdv_intel_dp_start_link_train(encoder);
+ tries = 0;
+ cr_tries++;
+ continue;
+ }
+
+ /* Compute new intel_dp->train_set as requested by target */
+ cdv_intel_get_adjust_train(encoder);
+ ++tries;
+
+ }
+
+ reg = DP | DP_LINK_TRAIN_OFF;
+
+ REG_WRITE(intel_dp->output_reg, reg);
+ REG_READ(intel_dp->output_reg);
+ cdv_intel_dp_aux_native_write_1(encoder,
+ DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
+ }
+
+ static void
+ cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ uint32_t DP = intel_dp->DP;
+
+ if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
+ return;
+
+ DRM_DEBUG_KMS("\n");
+
+
+ {
+ DP &= ~DP_LINK_TRAIN_MASK;
+ REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
+ }
+ REG_READ(intel_dp->output_reg);
+
+ msleep(17);
+
+ REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
+ REG_READ(intel_dp->output_reg);
+ }
+
+ static enum drm_connector_status
+ cdv_dp_detect(struct psb_intel_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ enum drm_connector_status status;
+
+ status = connector_status_disconnected;
+ if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
+ sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
+ {
+ if (intel_dp->dpcd[DP_DPCD_REV] != 0)
+ status = connector_status_connected;
+ }
+ if (status == connector_status_connected)
+ DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
+ intel_dp->dpcd[0], intel_dp->dpcd[1],
+ intel_dp->dpcd[2], intel_dp->dpcd[3]);
+ return status;
+ }
+
+ /**
+ * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
+ *
+ * \return true if DP port is connected.
+ * \return false if DP port is disconnected.
+ */
+ static enum drm_connector_status
+ cdv_intel_dp_detect(struct drm_connector *connector, bool force)
+ {
+ struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ enum drm_connector_status status;
+ struct edid *edid = NULL;
+ int edp = is_edp(encoder);
+
+ intel_dp->has_audio = false;
+
+ if (edp)
+ cdv_intel_edp_panel_vdd_on(encoder);
+ status = cdv_dp_detect(encoder);
+ if (status != connector_status_connected) {
+ if (edp)
+ cdv_intel_edp_panel_vdd_off(encoder);
+ return status;
+ }
+
+ if (intel_dp->force_audio) {
+ intel_dp->has_audio = intel_dp->force_audio > 0;
+ } else {
+ edid = drm_get_edid(connector, &intel_dp->adapter);
+ if (edid) {
+ intel_dp->has_audio = drm_detect_monitor_audio(edid);
+ kfree(edid);
+ }
+ }
+ if (edp)
+ cdv_intel_edp_panel_vdd_off(encoder);
+
+ return connector_status_connected;
+ }
+
+ static int cdv_intel_dp_get_modes(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct edid *edid = NULL;
+ int ret = 0;
+ int edp = is_edp(intel_encoder);
+
+
+ edid = drm_get_edid(connector, &intel_dp->adapter);
+ if (edid) {
+ drm_mode_connector_update_edid_property(connector, edid);
+ ret = drm_add_edid_modes(connector, edid);
+ kfree(edid);
+ }
+
+ if (is_edp(intel_encoder)) {
+ struct drm_device *dev = connector->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+ cdv_intel_edp_panel_vdd_off(intel_encoder);
+ if (ret) {
+ if (edp && !intel_dp->panel_fixed_mode) {
+ struct drm_display_mode *newmode;
+ list_for_each_entry(newmode, &connector->probed_modes,
+ head) {
+ if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
+ intel_dp->panel_fixed_mode =
+ drm_mode_duplicate(dev, newmode);
+ break;
+ }
+ }
+ }
+
+ return ret;
+ }
+ if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
+ intel_dp->panel_fixed_mode =
+ drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
+ if (intel_dp->panel_fixed_mode) {
+ intel_dp->panel_fixed_mode->type |=
+ DRM_MODE_TYPE_PREFERRED;
+ }
+ }
+ if (intel_dp->panel_fixed_mode != NULL) {
+ struct drm_display_mode *mode;
+ mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
+ drm_mode_probed_add(connector, mode);
+ return 1;
+ }
+ }
+
+ return ret;
+ }
+
+ static bool
+ cdv_intel_dp_detect_audio(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ struct edid *edid;
+ bool has_audio = false;
+ int edp = is_edp(encoder);
+
+ if (edp)
+ cdv_intel_edp_panel_vdd_on(encoder);
+
+ edid = drm_get_edid(connector, &intel_dp->adapter);
+ if (edid) {
+ has_audio = drm_detect_monitor_audio(edid);
+ kfree(edid);
+ }
+ if (edp)
+ cdv_intel_edp_panel_vdd_off(encoder);
+
+ return has_audio;
+ }
+
+ static int
+ cdv_intel_dp_set_property(struct drm_connector *connector,
+ struct drm_property *property,
+ uint64_t val)
+ {
+ struct drm_psb_private *dev_priv = connector->dev->dev_private;
+ struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret;
+
+ ret = drm_connector_property_set_value(connector, property, val);
+ if (ret)
+ return ret;
+
+ if (property == dev_priv->force_audio_property) {
+ int i = val;
+ bool has_audio;
+
+ if (i == intel_dp->force_audio)
+ return 0;
+
+ intel_dp->force_audio = i;
+
+ if (i == 0)
+ has_audio = cdv_intel_dp_detect_audio(connector);
+ else
+ has_audio = i > 0;
+
+ if (has_audio == intel_dp->has_audio)
+ return 0;
+
+ intel_dp->has_audio = has_audio;
+ goto done;
+ }
+
+ if (property == dev_priv->broadcast_rgb_property) {
+ if (val == !!intel_dp->color_range)
+ return 0;
+
+ intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
+ goto done;
+ }
+
+ return -EINVAL;
+
+ done:
+ if (encoder->base.crtc) {
+ struct drm_crtc *crtc = encoder->base.crtc;
+ drm_crtc_helper_set_mode(crtc, &crtc->mode,
+ crtc->x, crtc->y,
+ crtc->fb);
+ }
+
+ return 0;
+ }
+
+ static void
+ cdv_intel_dp_destroy(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+ psb_intel_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
+
+ if (is_edp(psb_intel_encoder)) {
+ /* cdv_intel_panel_destroy_backlight(connector->dev); */
+ if (intel_dp->panel_fixed_mode) {
+ kfree(intel_dp->panel_fixed_mode);
+ intel_dp->panel_fixed_mode = NULL;
+ }
+ }
+ i2c_del_adapter(&intel_dp->adapter);
+ drm_sysfs_connector_remove(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+ }
+
+ static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder)
+ {
+ drm_encoder_cleanup(encoder);
+ }
+
+ static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
+ .dpms = cdv_intel_dp_dpms,
+ .mode_fixup = cdv_intel_dp_mode_fixup,
+ .prepare = cdv_intel_dp_prepare,
+ .mode_set = cdv_intel_dp_mode_set,
+ .commit = cdv_intel_dp_commit,
+ };
+
+ static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .detect = cdv_intel_dp_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .set_property = cdv_intel_dp_set_property,
+ .destroy = cdv_intel_dp_destroy,
+ };
+
+ static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
+ .get_modes = cdv_intel_dp_get_modes,
+ .mode_valid = cdv_intel_dp_mode_valid,
+ .best_encoder = psb_intel_best_encoder,
+ };
+
+ static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
+ .destroy = cdv_intel_dp_encoder_destroy,
+ };
+
+
+ static void cdv_intel_dp_add_properties(struct drm_connector *connector)
+ {
+ cdv_intel_attach_force_audio_property(connector);
+ cdv_intel_attach_broadcast_rgb_property(connector);
+ }
+
+ /* check the VBT to see whether the eDP is on DP-D port */
+ static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct child_device_config *p_child;
+ int i;
+
+ if (!dev_priv->child_dev_num)
+ return false;
+
+ for (i = 0; i < dev_priv->child_dev_num; i++) {
+ p_child = dev_priv->child_dev + i;
+
+ if (p_child->dvo_port == PORT_IDPC &&
+ p_child->device_type == DEVICE_TYPE_eDP)
+ return true;
+ }
+ return false;
+ }
+
+ /* Cedarview display clock gating
+
+ We need this disable dot get correct behaviour while enabling
+ DP/eDP. TODO - investigate if we can turn it back to normality
+ after enabling */
+ static void cdv_disable_intel_clock_gating(struct drm_device *dev)
+ {
+ u32 reg_value;
+ reg_value = REG_READ(DSPCLK_GATE_D);
+
+ reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
+ DPUNIT_PIPEA_GATE_DISABLE |
+ DPCUNIT_CLOCK_GATE_DISABLE |
+ DPLSUNIT_CLOCK_GATE_DISABLE |
+ DPOUNIT_CLOCK_GATE_DISABLE |
+ DPIOUNIT_CLOCK_GATE_DISABLE);
+
+ REG_WRITE(DSPCLK_GATE_D, reg_value);
+
+ udelay(500);
+ }
+
+ void
+ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+ struct psb_intel_connector *psb_intel_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct cdv_intel_dp *intel_dp;
+ const char *name = NULL;
+ int type = DRM_MODE_CONNECTOR_DisplayPort;
+
+ psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+ if (!psb_intel_encoder)
+ return;
+ psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+ if (!psb_intel_connector)
+ goto err_connector;
+ intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
+ if (!intel_dp)
+ goto err_priv;
+
+ if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))
+ type = DRM_MODE_CONNECTOR_eDP;
+
+ connector = &psb_intel_connector->base;
+ encoder = &psb_intel_encoder->base;
+
+ drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
+ drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
+
+ psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+
+ if (type == DRM_MODE_CONNECTOR_DisplayPort)
+ psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+ else
+ psb_intel_encoder->type = INTEL_OUTPUT_EDP;
+
+
+ psb_intel_encoder->dev_priv=intel_dp;
+ intel_dp->encoder = psb_intel_encoder;
+ intel_dp->output_reg = output_reg;
+
+ drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
+ drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
+
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+
+ drm_sysfs_connector_add(connector);
+
+ /* Set up the DDC bus. */
+ switch (output_reg) {
+ case DP_B:
+ name = "DPDDC-B";
+ psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
+ break;
+ case DP_C:
+ name = "DPDDC-C";
+ psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
+ break;
+ }
+
+ cdv_disable_intel_clock_gating(dev);
+
+ cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
+ /* FIXME:fail check */
+ cdv_intel_dp_add_properties(connector);
+
+ if (is_edp(psb_intel_encoder)) {
+ int ret;
+ struct edp_power_seq cur;
+ u32 pp_on, pp_off, pp_div;
+ u32 pwm_ctrl;
+
+ pp_on = REG_READ(PP_CONTROL);
+ pp_on &= ~PANEL_UNLOCK_MASK;
+ pp_on |= PANEL_UNLOCK_REGS;
+
+ REG_WRITE(PP_CONTROL, pp_on);
+
+ pwm_ctrl = REG_READ(BLC_PWM_CTL2);
+ pwm_ctrl |= PWM_PIPE_B;
+ REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
+
+ pp_on = REG_READ(PP_ON_DELAYS);
+ pp_off = REG_READ(PP_OFF_DELAYS);
+ pp_div = REG_READ(PP_DIVISOR);
+
+ /* Pull timing values out of registers */
+ cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
+ PANEL_POWER_UP_DELAY_SHIFT;
+
+ cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
+ PANEL_LIGHT_ON_DELAY_SHIFT;
+
+ cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
+ PANEL_LIGHT_OFF_DELAY_SHIFT;
+
+ cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
+ PANEL_POWER_DOWN_DELAY_SHIFT;
+
+ cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT);
+
+ DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+ cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
+
+
+ intel_dp->panel_power_up_delay = cur.t1_t3 / 10;
+ intel_dp->backlight_on_delay = cur.t8 / 10;
+ intel_dp->backlight_off_delay = cur.t9 / 10;
+ intel_dp->panel_power_down_delay = cur.t10 / 10;
+ intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;
+
+ DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
+ intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
+ intel_dp->panel_power_cycle_delay);
+
+ DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
+ intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
+
+
+ cdv_intel_edp_panel_vdd_on(psb_intel_encoder);
+ ret = cdv_intel_dp_aux_native_read(psb_intel_encoder, DP_DPCD_REV,
+ intel_dp->dpcd,
+ sizeof(intel_dp->dpcd));
+ cdv_intel_edp_panel_vdd_off(psb_intel_encoder);
+ if (ret == 0) {
+ /* if this fails, presume the device is a ghost */
+ DRM_INFO("failed to retrieve link info, disabling eDP\n");
+ cdv_intel_dp_encoder_destroy(encoder);
+ cdv_intel_dp_destroy(connector);
+ goto err_priv;
+ } else {
+ DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
+ intel_dp->dpcd[0], intel_dp->dpcd[1],
+ intel_dp->dpcd[2], intel_dp->dpcd[3]);
+
+ }
+ /* The CDV reference driver moves pnale backlight setup into the displays that
+ have a backlight: this is a good idea and one we should probably adopt, however
+ we need to migrate all the drivers before we can do that */
+ /*cdv_intel_panel_setup_backlight(dev); */
+ }
+ return;
+
+ err_priv:
+ kfree(psb_intel_connector);
+ err_connector:
+ kfree(psb_intel_encoder);
+ }
* SOFTWARE.
*/
- #include <drm/drmP.h>
- #define NV_DEBUG_NOTRACE
- #include "nouveau_drv.h"
- #include "nouveau_hw.h"
- #include "nouveau_encoder.h"
- #include "nouveau_gpio.h"
-
- #include <linux/io-mapping.h>
- #include <linux/firmware.h>
-
- /* these defines are made up */
- #define NV_CIO_CRE_44_HEADA 0x0
- #define NV_CIO_CRE_44_HEADB 0x3
- #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
-
- #define EDID1_LEN 128
-
- #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
- #define LOG_OLD_VALUE(x)
-
- struct init_exec {
- bool execute;
- bool repeat;
- };
-
- static bool nv_cksum(const uint8_t *data, unsigned int length)
- {
- /*
- * There's a few checksums in the BIOS, so here's a generic checking
- * function.
- */
- int i;
- uint8_t sum = 0;
-
- for (i = 0; i < length; i++)
- sum += data[i];
-
- if (sum)
- return true;
-
- return false;
- }
-
- static int
- score_vbios(struct nvbios *bios, const bool writeable)
- {
- if (!bios->data || bios->data[0] != 0x55 || bios->data[1] != 0xAA) {
- NV_TRACEWARN(bios->dev, "... BIOS signature not found\n");
- return 0;
- }
-
- if (nv_cksum(bios->data, bios->data[2] * 512)) {
- NV_TRACEWARN(bios->dev, "... BIOS checksum invalid\n");
- /* if a ro image is somewhat bad, it's probably all rubbish */
- return writeable ? 2 : 1;
- }
-
- NV_TRACE(bios->dev, "... appears to be valid\n");
- return 3;
- }
-
- static void
- bios_shadow_prom(struct nvbios *bios)
- {
- struct drm_device *dev = bios->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- u32 pcireg, access;
- u16 pcir;
- int i;
-
- /* enable access to rom */
- if (dev_priv->card_type >= NV_50)
- pcireg = 0x088050;
- else
- pcireg = NV_PBUS_PCI_NV_20;
- access = nv_mask(dev, pcireg, 0x00000001, 0x00000000);
-
- /* bail if no rom signature, with a workaround for a PROM reading
- * issue on some chipsets. the first read after a period of
- * inactivity returns the wrong result, so retry the first header
- * byte a few times before giving up as a workaround
- */
- i = 16;
- do {
- if (nv_rd08(dev, NV_PROM_OFFSET + 0) == 0x55)
- break;
- } while (i--);
-
- if (!i || nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
- goto out;
-
- /* additional check (see note below) - read PCI record header */
- pcir = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
- nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
- if (nv_rd08(dev, NV_PROM_OFFSET + pcir + 0) != 'P' ||
- nv_rd08(dev, NV_PROM_OFFSET + pcir + 1) != 'C' ||
- nv_rd08(dev, NV_PROM_OFFSET + pcir + 2) != 'I' ||
- nv_rd08(dev, NV_PROM_OFFSET + pcir + 3) != 'R')
- goto out;
-
- /* read entire bios image to system memory */
- bios->length = nv_rd08(dev, NV_PROM_OFFSET + 2) * 512;
- bios->data = kmalloc(bios->length, GFP_KERNEL);
- if (bios->data) {
- for (i = 0; i < bios->length; i++)
- bios->data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
- }
-
- out:
- /* disable access to rom */
- nv_wr32(dev, pcireg, access);
- }
-
- static void
- bios_shadow_pramin(struct nvbios *bios)
- {
- struct drm_device *dev = bios->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- u32 bar0 = 0;
- int i;
-
- if (dev_priv->card_type >= NV_50) {
- u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
- if (!addr) {
- addr = (u64)nv_rd32(dev, 0x001700) << 16;
- addr += 0xf0000;
- }
-
- bar0 = nv_mask(dev, 0x001700, 0xffffffff, addr >> 16);
- }
-
- /* bail if no rom signature */
- if (nv_rd08(dev, NV_PRAMIN_OFFSET + 0) != 0x55 ||
- nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
- goto out;
-
- bios->length = nv_rd08(dev, NV_PRAMIN_OFFSET + 2) * 512;
- bios->data = kmalloc(bios->length, GFP_KERNEL);
- if (bios->data) {
- for (i = 0; i < bios->length; i++)
- bios->data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
- }
-
- out:
- if (dev_priv->card_type >= NV_50)
- nv_wr32(dev, 0x001700, bar0);
- }
-
- static void
- bios_shadow_pci(struct nvbios *bios)
- {
- struct pci_dev *pdev = bios->dev->pdev;
- size_t length;
-
- if (!pci_enable_rom(pdev)) {
- void __iomem *rom = pci_map_rom(pdev, &length);
- if (rom && length) {
- bios->data = kmalloc(length, GFP_KERNEL);
- if (bios->data) {
- memcpy_fromio(bios->data, rom, length);
- bios->length = length;
- }
- }
- if (rom)
- pci_unmap_rom(pdev, rom);
-
- pci_disable_rom(pdev);
- }
- }
-
- static void
- bios_shadow_acpi(struct nvbios *bios)
- {
- struct pci_dev *pdev = bios->dev->pdev;
- int cnt = 65536 / ROM_BIOS_PAGE;
- int ret;
-
- if (!nouveau_acpi_rom_supported(pdev))
- return;
-
- bios->data = kmalloc(cnt * ROM_BIOS_PAGE, GFP_KERNEL);
- if (!bios->data)
- return;
-
- bios->length = 0;
- while (cnt--) {
- ret = nouveau_acpi_get_bios_chunk(bios->data, bios->length,
- ROM_BIOS_PAGE);
- if (ret != ROM_BIOS_PAGE)
- return;
-
- bios->length += ROM_BIOS_PAGE;
- }
- }
-
- struct methods {
- const char desc[8];
- void (*shadow)(struct nvbios *);
- const bool rw;
- int score;
- u32 size;
- u8 *data;
- };
-
- static bool
- bios_shadow(struct drm_device *dev)
- {
- struct methods shadow_methods[] = {
- { "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL },
- { "PROM", bios_shadow_prom, false, 0, 0, NULL },
- { "ACPI", bios_shadow_acpi, true, 0, 0, NULL },
- { "PCIROM", bios_shadow_pci, true, 0, 0, NULL },
- {}
- };
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvbios *bios = &dev_priv->vbios;
- struct methods *mthd, *best;
- const struct firmware *fw;
- char fname[32];
- int ret;
-
- if (nouveau_vbios) {
- /* try to match one of the built-in methods */
- mthd = shadow_methods;
- do {
- if (strcasecmp(nouveau_vbios, mthd->desc))
- continue;
- NV_INFO(dev, "VBIOS source: %s\n", mthd->desc);
-
- mthd->shadow(bios);
- mthd->score = score_vbios(bios, mthd->rw);
- if (mthd->score)
- return true;
- } while ((++mthd)->shadow);
-
- /* attempt to load firmware image */
- snprintf(fname, sizeof(fname), "nouveau/%s", nouveau_vbios);
- ret = request_firmware(&fw, fname, &dev->pdev->dev);
- if (ret == 0) {
- bios->length = fw->size;
- bios->data = kmemdup(fw->data, fw->size, GFP_KERNEL);
- release_firmware(fw);
-
- NV_INFO(dev, "VBIOS image: %s\n", nouveau_vbios);
- if (score_vbios(bios, 1))
- return true;
-
- kfree(bios->data);
- bios->data = NULL;
- }
-
- NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
- }
-
- mthd = shadow_methods;
- do {
- NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc);
- mthd->shadow(bios);
- mthd->score = score_vbios(bios, mthd->rw);
- mthd->size = bios->length;
- mthd->data = bios->data;
- bios->data = NULL;
- } while (mthd->score != 3 && (++mthd)->shadow);
-
- mthd = shadow_methods;
- best = mthd;
- do {
- if (mthd->score > best->score) {
- kfree(best->data);
- best = mthd;
- }
- } while ((++mthd)->shadow);
-
- if (best->score) {
- NV_TRACE(dev, "Using VBIOS from %s\n", best->desc);
- bios->length = best->size;
- bios->data = best->data;
- return true;
- }
-
- NV_ERROR(dev, "No valid VBIOS image found\n");
- return false;
- }
-
- struct init_tbl_entry {
- char *name;
- uint8_t id;
- /* Return:
- * > 0: success, length of opcode
- * 0: success, but abort further parsing of table (INIT_DONE etc)
- * < 0: failure, table parsing will be aborted
- */
- int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
- };
-
- static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
-
- #define MACRO_INDEX_SIZE 2
- #define MACRO_SIZE 8
- #define CONDITION_SIZE 12
- #define IO_FLAG_CONDITION_SIZE 9
- #define IO_CONDITION_SIZE 5
- #define MEM_INIT_SIZE 66
-
- static void still_alive(void)
- {
- #if 0
- sync();
- mdelay(2);
- #endif
- }
-
- static uint32_t
- munge_reg(struct nvbios *bios, uint32_t reg)
- {
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- struct dcb_entry *dcbent = bios->display.output;
-
- if (dev_priv->card_type < NV_50)
- return reg;
-
- if (reg & 0x80000000) {
- BUG_ON(bios->display.crtc < 0);
- reg += bios->display.crtc * 0x800;
- }
-
- if (reg & 0x40000000) {
- BUG_ON(!dcbent);
-
- reg += (ffs(dcbent->or) - 1) * 0x800;
- if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
- reg += 0x00000080;
- }
-
- reg &= ~0xe0000000;
- return reg;
- }
-
- static int
- valid_reg(struct nvbios *bios, uint32_t reg)
- {
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- struct drm_device *dev = bios->dev;
-
- /* C51 has misaligned regs on purpose. Marvellous */
- if (reg & 0x2 ||
- (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
- NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
-
- /* warn on C51 regs that haven't been verified accessible in tracing */
- if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
- reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
- NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
- reg);
-
- if (reg >= (8*1024*1024)) {
- NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
- return 0;
- }
-
- return 1;
- }
-
- static bool
- valid_idx_port(struct nvbios *bios, uint16_t port)
- {
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- struct drm_device *dev = bios->dev;
-
- /*
- * If adding more ports here, the read/write functions below will need
- * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
- * used for the port in question
- */
- if (dev_priv->card_type < NV_50) {
- if (port == NV_CIO_CRX__COLOR)
- return true;
- if (port == NV_VIO_SRX)
- return true;
- } else {
- if (port == NV_CIO_CRX__COLOR)
- return true;
- }
-
- NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
- port);
-
- return false;
- }
-
- static bool
- valid_port(struct nvbios *bios, uint16_t port)
- {
- struct drm_device *dev = bios->dev;
-
- /*
- * If adding more ports here, the read/write functions below will need
- * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
- * used for the port in question
- */
- if (port == NV_VIO_VSE2)
- return true;
-
- NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
-
- return false;
- }
-
- static uint32_t
- bios_rd32(struct nvbios *bios, uint32_t reg)
- {
- uint32_t data;
-
- reg = munge_reg(bios, reg);
- if (!valid_reg(bios, reg))
- return 0;
-
- /*
- * C51 sometimes uses regs with bit0 set in the address. For these
- * cases there should exist a translation in a BIOS table to an IO
- * port address which the BIOS uses for accessing the reg
- *
- * These only seem to appear for the power control regs to a flat panel,
- * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
- * for 0x1308 and 0x1310 are used - hence the mask below. An S3
- * suspend-resume mmio trace from a C51 will be required to see if this
- * is true for the power microcode in 0x14.., or whether the direct IO
- * port access method is needed
- */
- if (reg & 0x1)
- reg &= ~0x1;
-
- data = nv_rd32(bios->dev, reg);
-
- BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
-
- return data;
- }
-
- static void
- bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
- {
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
-
- reg = munge_reg(bios, reg);
- if (!valid_reg(bios, reg))
- return;
-
- /* see note in bios_rd32 */
- if (reg & 0x1)
- reg &= 0xfffffffe;
-
- LOG_OLD_VALUE(bios_rd32(bios, reg));
- BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
-
- if (dev_priv->vbios.execute) {
- still_alive();
- nv_wr32(bios->dev, reg, data);
- }
- }
-
- static uint8_t
- bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
- {
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- struct drm_device *dev = bios->dev;
- uint8_t data;
-
- if (!valid_idx_port(bios, port))
- return 0;
-
- if (dev_priv->card_type < NV_50) {
- if (port == NV_VIO_SRX)
- data = NVReadVgaSeq(dev, bios->state.crtchead, index);
- else /* assume NV_CIO_CRX__COLOR */
- data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
- } else {
- uint32_t data32;
-
- data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
- data = (data32 >> ((index & 3) << 3)) & 0xff;
- }
-
- BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
- "Head: 0x%02X, Data: 0x%02X\n",
- port, index, bios->state.crtchead, data);
- return data;
- }
-
- static void
- bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
- {
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- struct drm_device *dev = bios->dev;
-
- if (!valid_idx_port(bios, port))
- return;
-
- /*
- * The current head is maintained in the nvbios member state.crtchead.
- * We trap changes to CR44 and update the head variable and hence the
- * register set written.
- * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
- * of the write, and to head1 after the write
- */
- if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
- data != NV_CIO_CRE_44_HEADB)
- bios->state.crtchead = 0;
-
- LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
- BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
- "Head: 0x%02X, Data: 0x%02X\n",
- port, index, bios->state.crtchead, data);
-
- if (bios->execute && dev_priv->card_type < NV_50) {
- still_alive();
- if (port == NV_VIO_SRX)
- NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
- else /* assume NV_CIO_CRX__COLOR */
- NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
- } else
- if (bios->execute) {
- uint32_t data32, shift = (index & 3) << 3;
-
- still_alive();
-
- data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
- data32 &= ~(0xff << shift);
- data32 |= (data << shift);
- bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
- }
-
- if (port == NV_CIO_CRX__COLOR &&
- index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
- bios->state.crtchead = 1;
- }
-
- static uint8_t
- bios_port_rd(struct nvbios *bios, uint16_t port)
- {
- uint8_t data, head = bios->state.crtchead;
-
- if (!valid_port(bios, port))
- return 0;
-
- data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
-
- BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
- port, head, data);
-
- return data;
- }
-
- static void
- bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
- {
- int head = bios->state.crtchead;
-
- if (!valid_port(bios, port))
- return;
-
- LOG_OLD_VALUE(bios_port_rd(bios, port));
- BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
- port, head, data);
-
- if (!bios->execute)
- return;
-
- still_alive();
- NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
- }
-
- static bool
- io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
- {
- /*
- * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
- * for the CRTC index; 1 byte for the mask to apply to the value
- * retrieved from the CRTC; 1 byte for the shift right to apply to the
- * masked CRTC value; 2 bytes for the offset to the flag array, to
- * which the shifted value is added; 1 byte for the mask applied to the
- * value read from the flag array; and 1 byte for the value to compare
- * against the masked byte from the flag table.
- */
-
- uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
- uint16_t crtcport = ROM16(bios->data[condptr]);
- uint8_t crtcindex = bios->data[condptr + 2];
- uint8_t mask = bios->data[condptr + 3];
- uint8_t shift = bios->data[condptr + 4];
- uint16_t flagarray = ROM16(bios->data[condptr + 5]);
- uint8_t flagarraymask = bios->data[condptr + 7];
- uint8_t cmpval = bios->data[condptr + 8];
- uint8_t data;
-
- BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
- "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
- "Cmpval: 0x%02X\n",
- offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
-
- data = bios_idxprt_rd(bios, crtcport, crtcindex);
-
- data = bios->data[flagarray + ((data & mask) >> shift)];
- data &= flagarraymask;
-
- BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
- offset, data, cmpval);
-
- return (data == cmpval);
- }
-
- static bool
- bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
- {
- /*
- * The condition table entry has 4 bytes for the address of the
- * register to check, 4 bytes for a mask to apply to the register and
- * 4 for a test comparison value
- */
-
- uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
- uint32_t reg = ROM32(bios->data[condptr]);
- uint32_t mask = ROM32(bios->data[condptr + 4]);
- uint32_t cmpval = ROM32(bios->data[condptr + 8]);
- uint32_t data;
-
- BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
- offset, cond, reg, mask);
-
- data = bios_rd32(bios, reg) & mask;
-
- BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
- offset, data, cmpval);
-
- return (data == cmpval);
- }
-
- static bool
- io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
- {
- /*
- * The IO condition entry has 2 bytes for the IO port address; 1 byte
- * for the index to write to io_port; 1 byte for the mask to apply to
- * the byte read from io_port+1; and 1 byte for the value to compare
- * against the masked byte.
- */
-
- uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
- uint16_t io_port = ROM16(bios->data[condptr]);
- uint8_t port_index = bios->data[condptr + 2];
- uint8_t mask = bios->data[condptr + 3];
- uint8_t cmpval = bios->data[condptr + 4];
-
- uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
-
- BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
- offset, data, cmpval);
-
- return (data == cmpval);
- }
-
- static int
- nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
- {
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pll_vals pll;
- struct pll_lims pll_limits;
- u32 ctrl, mask, coef;
- int ret;
-
- ret = get_pll_limits(dev, reg, &pll_limits);
- if (ret)
- return ret;
-
- clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
- if (!clk)
- return -ERANGE;
-
- coef = pll.N1 << 8 | pll.M1;
- ctrl = pll.log2P << 16;
- mask = 0x00070000;
- if (reg == 0x004008) {
- mask |= 0x01f80000;
- ctrl |= (pll_limits.log2p_bias << 19);
- ctrl |= (pll.log2P << 22);
- }
-
- if (!dev_priv->vbios.execute)
- return 0;
-
- nv_mask(dev, reg + 0, mask, ctrl);
- nv_wr32(dev, reg + 4, coef);
- return 0;
- }
-
- static int
- setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
- {
- struct drm_device *dev = bios->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- /* clk in kHz */
- struct pll_lims pll_lim;
- struct nouveau_pll_vals pllvals;
- int ret;
-
- if (dev_priv->card_type >= NV_50)
- return nv50_pll_set(dev, reg, clk);
-
- /* high regs (such as in the mac g5 table) are not -= 4 */
- ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
- if (ret)
- return ret;
-
- clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
- if (!clk)
- return -ERANGE;
-
- if (bios->execute) {
- still_alive();
- nouveau_hw_setpll(dev, reg, &pllvals);
- }
-
- return 0;
- }
-
- static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
- {
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvbios *bios = &dev_priv->vbios;
-
- /*
- * For the results of this function to be correct, CR44 must have been
- * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
- * and the DCB table parsed, before the script calling the function is
- * run. run_digital_op_script is example of how to do such setup
- */
-
- uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
-
- if (dcb_entry > bios->dcb.entries) {
- NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
- "(%02X)\n", dcb_entry);
- dcb_entry = 0x7f; /* unused / invalid marker */
- }
-
- return dcb_entry;
- }
-
- static struct nouveau_i2c_chan *
- init_i2c_device_find(struct drm_device *dev, int i2c_index)
- {
- if (i2c_index == 0xff) {
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct dcb_table *dcb = &dev_priv->vbios.dcb;
- /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
- int idx = dcb_entry_idx_from_crtchead(dev);
-
- i2c_index = NV_I2C_DEFAULT(0);
- if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
- i2c_index = NV_I2C_DEFAULT(1);
- }
-
- return nouveau_i2c_find(dev, i2c_index);
- }
-
- static uint32_t
- get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
- {
- /*
- * For mlv < 0x80, it is an index into a table of TMDS base addresses.
- * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
- * CR58 for CR57 = 0 to index a table of offsets to the basic
- * 0x6808b0 address.
- * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
- * CR58 for CR57 = 0 to index a table of offsets to the basic
- * 0x6808b0 address, and then flip the offset by 8.
- */
-
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvbios *bios = &dev_priv->vbios;
- const int pramdac_offset[13] = {
- 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
- const uint32_t pramdac_table[4] = {
- 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
-
- if (mlv >= 0x80) {
- int dcb_entry, dacoffset;
-
- /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
- dcb_entry = dcb_entry_idx_from_crtchead(dev);
- if (dcb_entry == 0x7f)
- return 0;
- dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
- if (mlv == 0x81)
- dacoffset ^= 8;
- return 0x6808b0 + dacoffset;
- } else {
- if (mlv >= ARRAY_SIZE(pramdac_table)) {
- NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
- mlv);
- return 0;
- }
- return pramdac_table[mlv];
- }
- }
-
- static int
- init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): CRTC port
- * offset + 3 (8 bit): CRTC index
- * offset + 4 (8 bit): mask
- * offset + 5 (8 bit): shift
- * offset + 6 (8 bit): count
- * offset + 7 (32 bit): register
- * offset + 11 (32 bit): configuration 1
- * ...
- *
- * Starting at offset + 11 there are "count" 32 bit values.
- * To find out which value to use read index "CRTC index" on "CRTC
- * port", AND this value with "mask" and then bit shift right "shift"
- * bits. Read the appropriate value using this index and write to
- * "register"
- */
-
- uint16_t crtcport = ROM16(bios->data[offset + 1]);
- uint8_t crtcindex = bios->data[offset + 3];
- uint8_t mask = bios->data[offset + 4];
- uint8_t shift = bios->data[offset + 5];
- uint8_t count = bios->data[offset + 6];
- uint32_t reg = ROM32(bios->data[offset + 7]);
- uint8_t config;
- uint32_t configval;
- int len = 11 + count * 4;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
- "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
- offset, crtcport, crtcindex, mask, shift, count, reg);
-
- config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
- if (config > count) {
- NV_ERROR(bios->dev,
- "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
- offset, config, count);
- return len;
- }
-
- configval = ROM32(bios->data[offset + 11 + config * 4]);
-
- BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
-
- bios_wr32(bios, reg, configval);
-
- return len;
- }
-
- static int
- init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_REPEAT opcode: 0x33 ('3')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): count
- *
- * Execute script following this opcode up to INIT_REPEAT_END
- * "count" times
- */
-
- uint8_t count = bios->data[offset + 1];
- uint8_t i;
-
- /* no iexec->execute check by design */
-
- BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
- offset, count);
-
- iexec->repeat = true;
-
- /*
- * count - 1, as the script block will execute once when we leave this
- * opcode -- this is compatible with bios behaviour as:
- * a) the block is always executed at least once, even if count == 0
- * b) the bios interpreter skips to the op following INIT_END_REPEAT,
- * while we don't
- */
- for (i = 0; i < count - 1; i++)
- parse_init_table(bios, offset + 2, iexec);
-
- iexec->repeat = false;
-
- return 2;
- }
-
- static int
- init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): CRTC port
- * offset + 3 (8 bit): CRTC index
- * offset + 4 (8 bit): mask
- * offset + 5 (8 bit): shift
- * offset + 6 (8 bit): IO flag condition index
- * offset + 7 (8 bit): count
- * offset + 8 (32 bit): register
- * offset + 12 (16 bit): frequency 1
- * ...
- *
- * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
- * Set PLL register "register" to coefficients for frequency n,
- * selected by reading index "CRTC index" of "CRTC port" ANDed with
- * "mask" and shifted right by "shift".
- *
- * If "IO flag condition index" > 0, and condition met, double
- * frequency before setting it.
- */
-
- uint16_t crtcport = ROM16(bios->data[offset + 1]);
- uint8_t crtcindex = bios->data[offset + 3];
- uint8_t mask = bios->data[offset + 4];
- uint8_t shift = bios->data[offset + 5];
- int8_t io_flag_condition_idx = bios->data[offset + 6];
- uint8_t count = bios->data[offset + 7];
- uint32_t reg = ROM32(bios->data[offset + 8]);
- uint8_t config;
- uint16_t freq;
- int len = 12 + count * 2;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
- "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
- "Count: 0x%02X, Reg: 0x%08X\n",
- offset, crtcport, crtcindex, mask, shift,
- io_flag_condition_idx, count, reg);
-
- config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
- if (config > count) {
- NV_ERROR(bios->dev,
- "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
- offset, config, count);
- return len;
- }
-
- freq = ROM16(bios->data[offset + 12 + config * 2]);
-
- if (io_flag_condition_idx > 0) {
- if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
- BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
- "frequency doubled\n", offset);
- freq *= 2;
- } else
- BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
- "frequency unchanged\n", offset);
- }
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
- offset, reg, config, freq);
-
- setPLL(bios, reg, freq * 10);
-
- return len;
- }
-
- static int
- init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_END_REPEAT opcode: 0x36 ('6')
- *
- * offset (8 bit): opcode
- *
- * Marks the end of the block for INIT_REPEAT to repeat
- */
-
- /* no iexec->execute check by design */
-
- /*
- * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
- * we're not in repeat mode
- */
- if (iexec->repeat)
- return 0;
-
- return 1;
- }
-
- static int
- init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_COPY opcode: 0x37 ('7')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (8 bit): shift
- * offset + 6 (8 bit): srcmask
- * offset + 7 (16 bit): CRTC port
- * offset + 9 (8 bit): CRTC index
- * offset + 10 (8 bit): mask
- *
- * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
- * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
- * port
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint8_t shift = bios->data[offset + 5];
- uint8_t srcmask = bios->data[offset + 6];
- uint16_t crtcport = ROM16(bios->data[offset + 7]);
- uint8_t crtcindex = bios->data[offset + 9];
- uint8_t mask = bios->data[offset + 10];
- uint32_t data;
- uint8_t crtcdata;
-
- if (!iexec->execute)
- return 11;
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
- "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
- offset, reg, shift, srcmask, crtcport, crtcindex, mask);
-
- data = bios_rd32(bios, reg);
-
- if (shift < 0x80)
- data >>= shift;
- else
- data <<= (0x100 - shift);
-
- data &= srcmask;
-
- crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
- crtcdata |= (uint8_t)data;
- bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
-
- return 11;
- }
-
- static int
- init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_NOT opcode: 0x38 ('8')
- *
- * offset (8 bit): opcode
- *
- * Invert the current execute / no-execute condition (i.e. "else")
- */
- if (iexec->execute)
- BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
- else
- BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
-
- iexec->execute = !iexec->execute;
- return 1;
- }
-
- static int
- init_io_flag_condition(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): condition number
- *
- * Check condition "condition number" in the IO flag condition table.
- * If condition not met skip subsequent opcodes until condition is
- * inverted (INIT_NOT), or we hit INIT_RESUME
- */
-
- uint8_t cond = bios->data[offset + 1];
-
- if (!iexec->execute)
- return 2;
-
- if (io_flag_condition_met(bios, offset, cond))
- BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
- else {
- BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
- iexec->execute = false;
- }
-
- return 2;
- }
-
- static int
- init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_DP_CONDITION opcode: 0x3A ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): "sub" opcode
- * offset + 2 (8 bit): unknown
- *
- */
-
- struct dcb_entry *dcb = bios->display.output;
- struct drm_device *dev = bios->dev;
- uint8_t cond = bios->data[offset + 1];
- uint8_t *table, *entry;
-
- BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
-
- if (!iexec->execute)
- return 3;
-
- table = nouveau_dp_bios_data(dev, dcb, &entry);
- if (!table)
- return 3;
-
- switch (cond) {
- case 0:
- entry = dcb_conn(dev, dcb->connector);
- if (!entry || entry[0] != DCB_CONNECTOR_eDP)
- iexec->execute = false;
- break;
- case 1:
- case 2:
- if ((table[0] < 0x40 && !(entry[5] & cond)) ||
- (table[0] == 0x40 && !(entry[4] & cond)))
- iexec->execute = false;
- break;
- case 5:
- {
- struct nouveau_i2c_chan *auxch;
- int ret;
-
- auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
- if (!auxch) {
- NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
- return 3;
- }
-
- ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
- if (ret) {
- NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
- return 3;
- }
-
- if (!(cond & 1))
- iexec->execute = false;
- }
- break;
- default:
- NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
- break;
- }
-
- if (iexec->execute)
- BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
- else
- BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
-
- return 3;
- }
-
- static int
- init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_3B opcode: 0x3B ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): crtc index
- *
- */
-
- uint8_t or = ffs(bios->display.output->or) - 1;
- uint8_t index = bios->data[offset + 1];
- uint8_t data;
-
- if (!iexec->execute)
- return 2;
-
- data = bios_idxprt_rd(bios, 0x3d4, index);
- bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
- return 2;
- }
-
- static int
- init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_3C opcode: 0x3C ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): crtc index
- *
- */
-
- uint8_t or = ffs(bios->display.output->or) - 1;
- uint8_t index = bios->data[offset + 1];
- uint8_t data;
-
- if (!iexec->execute)
- return 2;
-
- data = bios_idxprt_rd(bios, 0x3d4, index);
- bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
- return 2;
- }
-
- static int
- init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): control register
- * offset + 5 (32 bit): data register
- * offset + 9 (32 bit): mask
- * offset + 13 (32 bit): data
- * offset + 17 (8 bit): count
- * offset + 18 (8 bit): address 1
- * offset + 19 (8 bit): data 1
- * ...
- *
- * For each of "count" address and data pairs, write "data n" to
- * "data register", read the current value of "control register",
- * and write it back once ANDed with "mask", ORed with "data",
- * and ORed with "address n"
- */
-
- uint32_t controlreg = ROM32(bios->data[offset + 1]);
- uint32_t datareg = ROM32(bios->data[offset + 5]);
- uint32_t mask = ROM32(bios->data[offset + 9]);
- uint32_t data = ROM32(bios->data[offset + 13]);
- uint8_t count = bios->data[offset + 17];
- int len = 18 + count * 2;
- uint32_t value;
- int i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
- "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
- offset, controlreg, datareg, mask, data, count);
-
- for (i = 0; i < count; i++) {
- uint8_t instaddress = bios->data[offset + 18 + i * 2];
- uint8_t instdata = bios->data[offset + 19 + i * 2];
-
- BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
- offset, instaddress, instdata);
-
- bios_wr32(bios, datareg, instdata);
- value = bios_rd32(bios, controlreg) & mask;
- value |= data;
- value |= instaddress;
- bios_wr32(bios, controlreg, value);
- }
-
- return len;
- }
-
- static int
- init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): CRTC port
- * offset + 3 (8 bit): CRTC index
- * offset + 4 (8 bit): mask
- * offset + 5 (8 bit): shift
- * offset + 6 (8 bit): count
- * offset + 7 (32 bit): register
- * offset + 11 (32 bit): frequency 1
- * ...
- *
- * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
- * Set PLL register "register" to coefficients for frequency n,
- * selected by reading index "CRTC index" of "CRTC port" ANDed with
- * "mask" and shifted right by "shift".
- */
-
- uint16_t crtcport = ROM16(bios->data[offset + 1]);
- uint8_t crtcindex = bios->data[offset + 3];
- uint8_t mask = bios->data[offset + 4];
- uint8_t shift = bios->data[offset + 5];
- uint8_t count = bios->data[offset + 6];
- uint32_t reg = ROM32(bios->data[offset + 7]);
- int len = 11 + count * 4;
- uint8_t config;
- uint32_t freq;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
- "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
- offset, crtcport, crtcindex, mask, shift, count, reg);
-
- if (!reg)
- return len;
-
- config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
- if (config > count) {
- NV_ERROR(bios->dev,
- "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
- offset, config, count);
- return len;
- }
-
- freq = ROM32(bios->data[offset + 11 + config * 4]);
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
- offset, reg, config, freq);
-
- setPLL(bios, reg, freq);
-
- return len;
- }
-
- static int
- init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_PLL2 opcode: 0x4B ('K')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (32 bit): freq
- *
- * Set PLL register "register" to coefficients for frequency "freq"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint32_t freq = ROM32(bios->data[offset + 5]);
-
- if (!iexec->execute)
- return 9;
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
- offset, reg, freq);
-
- setPLL(bios, reg, freq);
- return 9;
- }
-
- static int
- init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_I2C_BYTE opcode: 0x4C ('L')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): DCB I2C table entry index
- * offset + 2 (8 bit): I2C slave address
- * offset + 3 (8 bit): count
- * offset + 4 (8 bit): I2C register 1
- * offset + 5 (8 bit): mask 1
- * offset + 6 (8 bit): data 1
- * ...
- *
- * For each of "count" registers given by "I2C register n" on the device
- * addressed by "I2C slave address" on the I2C bus given by
- * "DCB I2C table entry index", read the register, AND the result with
- * "mask n" and OR it with "data n" before writing it back to the device
- */
-
- struct drm_device *dev = bios->dev;
- uint8_t i2c_index = bios->data[offset + 1];
- uint8_t i2c_address = bios->data[offset + 2] >> 1;
- uint8_t count = bios->data[offset + 3];
- struct nouveau_i2c_chan *chan;
- int len = 4 + count * 3;
- int ret, i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
- "Count: 0x%02X\n",
- offset, i2c_index, i2c_address, count);
-
- chan = init_i2c_device_find(dev, i2c_index);
- if (!chan) {
- NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
- return len;
- }
-
- for (i = 0; i < count; i++) {
- uint8_t reg = bios->data[offset + 4 + i * 3];
- uint8_t mask = bios->data[offset + 5 + i * 3];
- uint8_t data = bios->data[offset + 6 + i * 3];
- union i2c_smbus_data val;
-
- ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
- I2C_SMBUS_READ, reg,
- I2C_SMBUS_BYTE_DATA, &val);
- if (ret < 0) {
- NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
- return len;
- }
-
- BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
- "Mask: 0x%02X, Data: 0x%02X\n",
- offset, reg, val.byte, mask, data);
-
- if (!bios->execute)
- continue;
-
- val.byte &= mask;
- val.byte |= data;
- ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
- I2C_SMBUS_WRITE, reg,
- I2C_SMBUS_BYTE_DATA, &val);
- if (ret < 0) {
- NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
- return len;
- }
- }
-
- return len;
- }
-
- static int
- init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): DCB I2C table entry index
- * offset + 2 (8 bit): I2C slave address
- * offset + 3 (8 bit): count
- * offset + 4 (8 bit): I2C register 1
- * offset + 5 (8 bit): data 1
- * ...
- *
- * For each of "count" registers given by "I2C register n" on the device
- * addressed by "I2C slave address" on the I2C bus given by
- * "DCB I2C table entry index", set the register to "data n"
- */
-
- struct drm_device *dev = bios->dev;
- uint8_t i2c_index = bios->data[offset + 1];
- uint8_t i2c_address = bios->data[offset + 2] >> 1;
- uint8_t count = bios->data[offset + 3];
- struct nouveau_i2c_chan *chan;
- int len = 4 + count * 2;
- int ret, i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
- "Count: 0x%02X\n",
- offset, i2c_index, i2c_address, count);
-
- chan = init_i2c_device_find(dev, i2c_index);
- if (!chan) {
- NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
- return len;
- }
-
- for (i = 0; i < count; i++) {
- uint8_t reg = bios->data[offset + 4 + i * 2];
- union i2c_smbus_data val;
-
- val.byte = bios->data[offset + 5 + i * 2];
-
- BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
- offset, reg, val.byte);
-
- if (!bios->execute)
- continue;
-
- ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
- I2C_SMBUS_WRITE, reg,
- I2C_SMBUS_BYTE_DATA, &val);
- if (ret < 0) {
- NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
- return len;
- }
- }
-
- return len;
- }
-
- static int
- init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_I2C opcode: 0x4E ('N')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): DCB I2C table entry index
- * offset + 2 (8 bit): I2C slave address
- * offset + 3 (8 bit): count
- * offset + 4 (8 bit): data 1
- * ...
- *
- * Send "count" bytes ("data n") to the device addressed by "I2C slave
- * address" on the I2C bus given by "DCB I2C table entry index"
- */
-
- struct drm_device *dev = bios->dev;
- uint8_t i2c_index = bios->data[offset + 1];
- uint8_t i2c_address = bios->data[offset + 2] >> 1;
- uint8_t count = bios->data[offset + 3];
- int len = 4 + count;
- struct nouveau_i2c_chan *chan;
- struct i2c_msg msg;
- uint8_t data[256];
- int ret, i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
- "Count: 0x%02X\n",
- offset, i2c_index, i2c_address, count);
-
- chan = init_i2c_device_find(dev, i2c_index);
- if (!chan) {
- NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
- return len;
- }
-
- for (i = 0; i < count; i++) {
- data[i] = bios->data[offset + 4 + i];
-
- BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
- }
-
- if (bios->execute) {
- msg.addr = i2c_address;
- msg.flags = 0;
- msg.len = count;
- msg.buf = data;
- ret = i2c_transfer(&chan->adapter, &msg, 1);
- if (ret != 1) {
- NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
- return len;
- }
- }
-
- return len;
- }
-
- static int
- init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): magic lookup value
- * offset + 2 (8 bit): TMDS address
- * offset + 3 (8 bit): mask
- * offset + 4 (8 bit): data
- *
- * Read the data reg for TMDS address "TMDS address", AND it with mask
- * and OR it with data, then write it back
- * "magic lookup value" determines which TMDS base address register is
- * used -- see get_tmds_index_reg()
- */
-
- struct drm_device *dev = bios->dev;
- uint8_t mlv = bios->data[offset + 1];
- uint32_t tmdsaddr = bios->data[offset + 2];
- uint8_t mask = bios->data[offset + 3];
- uint8_t data = bios->data[offset + 4];
- uint32_t reg, value;
-
- if (!iexec->execute)
- return 5;
-
- BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
- "Mask: 0x%02X, Data: 0x%02X\n",
- offset, mlv, tmdsaddr, mask, data);
-
- reg = get_tmds_index_reg(bios->dev, mlv);
- if (!reg) {
- NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
- return 5;
- }
-
- bios_wr32(bios, reg,
- tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
- value = (bios_rd32(bios, reg + 4) & mask) | data;
- bios_wr32(bios, reg + 4, value);
- bios_wr32(bios, reg, tmdsaddr);
-
- return 5;
- }
-
- static int
- init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): magic lookup value
- * offset + 2 (8 bit): count
- * offset + 3 (8 bit): addr 1
- * offset + 4 (8 bit): data 1
- * ...
- *
- * For each of "count" TMDS address and data pairs write "data n" to
- * "addr n". "magic lookup value" determines which TMDS base address
- * register is used -- see get_tmds_index_reg()
- */
-
- struct drm_device *dev = bios->dev;
- uint8_t mlv = bios->data[offset + 1];
- uint8_t count = bios->data[offset + 2];
- int len = 3 + count * 2;
- uint32_t reg;
- int i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
- offset, mlv, count);
-
- reg = get_tmds_index_reg(bios->dev, mlv);
- if (!reg) {
- NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
- return len;
- }
-
- for (i = 0; i < count; i++) {
- uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
- uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
-
- bios_wr32(bios, reg + 4, tmdsdata);
- bios_wr32(bios, reg, tmdsaddr);
- }
-
- return len;
- }
-
- static int
- init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): CRTC index1
- * offset + 2 (8 bit): CRTC index2
- * offset + 3 (8 bit): baseaddr
- * offset + 4 (8 bit): count
- * offset + 5 (8 bit): data 1
- * ...
- *
- * For each of "count" address and data pairs, write "baseaddr + n" to
- * "CRTC index1" and "data n" to "CRTC index2"
- * Once complete, restore initial value read from "CRTC index1"
- */
- uint8_t crtcindex1 = bios->data[offset + 1];
- uint8_t crtcindex2 = bios->data[offset + 2];
- uint8_t baseaddr = bios->data[offset + 3];
- uint8_t count = bios->data[offset + 4];
- int len = 5 + count;
- uint8_t oldaddr, data;
- int i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
- "BaseAddr: 0x%02X, Count: 0x%02X\n",
- offset, crtcindex1, crtcindex2, baseaddr, count);
-
- oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
-
- for (i = 0; i < count; i++) {
- bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
- baseaddr + i);
- data = bios->data[offset + 5 + i];
- bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
- }
-
- bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
-
- return len;
- }
-
- static int
- init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_CR opcode: 0x52 ('R')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): CRTC index
- * offset + 2 (8 bit): mask
- * offset + 3 (8 bit): data
- *
- * Assign the value of at "CRTC index" ANDed with mask and ORed with
- * data back to "CRTC index"
- */
-
- uint8_t crtcindex = bios->data[offset + 1];
- uint8_t mask = bios->data[offset + 2];
- uint8_t data = bios->data[offset + 3];
- uint8_t value;
-
- if (!iexec->execute)
- return 4;
-
- BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
- offset, crtcindex, mask, data);
-
- value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
- value |= data;
- bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
-
- return 4;
- }
-
- static int
- init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_CR opcode: 0x53 ('S')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): CRTC index
- * offset + 2 (8 bit): value
- *
- * Assign "value" to CRTC register with index "CRTC index".
- */
-
- uint8_t crtcindex = ROM32(bios->data[offset + 1]);
- uint8_t data = bios->data[offset + 2];
-
- if (!iexec->execute)
- return 3;
-
- bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
-
- return 3;
- }
-
- static int
- init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): count
- * offset + 2 (8 bit): CRTC index 1
- * offset + 3 (8 bit): value 1
- * ...
- *
- * For "count", assign "value n" to CRTC register with index
- * "CRTC index n".
- */
-
- uint8_t count = bios->data[offset + 1];
- int len = 2 + count * 2;
- int i;
-
- if (!iexec->execute)
- return len;
-
- for (i = 0; i < count; i++)
- init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
-
- return len;
- }
-
- static int
- init_condition_time(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_CONDITION_TIME opcode: 0x56 ('V')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): condition number
- * offset + 2 (8 bit): retries / 50
- *
- * Check condition "condition number" in the condition table.
- * Bios code then sleeps for 2ms if the condition is not met, and
- * repeats up to "retries" times, but on one C51 this has proved
- * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
- * this, and bail after "retries" times, or 2s, whichever is less.
- * If still not met after retries, clear execution flag for this table.
- */
-
- uint8_t cond = bios->data[offset + 1];
- uint16_t retries = bios->data[offset + 2] * 50;
- unsigned cnt;
-
- if (!iexec->execute)
- return 3;
-
- if (retries > 100)
- retries = 100;
-
- BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
- offset, cond, retries);
-
- if (!bios->execute) /* avoid 2s delays when "faking" execution */
- retries = 1;
-
- for (cnt = 0; cnt < retries; cnt++) {
- if (bios_condition_met(bios, offset, cond)) {
- BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
- offset);
- break;
- } else {
- BIOSLOG(bios, "0x%04X: "
- "Condition not met, sleeping for 20ms\n",
- offset);
- mdelay(20);
- }
- }
-
- if (!bios_condition_met(bios, offset, cond)) {
- NV_WARN(bios->dev,
- "0x%04X: Condition still not met after %dms, "
- "skipping following opcodes\n", offset, 20 * retries);
- iexec->execute = false;
- }
-
- return 3;
- }
-
- static int
- init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_LTIME opcode: 0x57 ('V')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): time
- *
- * Sleep for "time" milliseconds.
- */
-
- unsigned time = ROM16(bios->data[offset + 1]);
-
- if (!iexec->execute)
- return 3;
-
- BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
- offset, time);
-
- mdelay(time);
-
- return 3;
- }
-
- static int
- init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): base register
- * offset + 5 (8 bit): count
- * offset + 6 (32 bit): value 1
- * ...
- *
- * Starting at offset + 6 there are "count" 32 bit values.
- * For "count" iterations set "base register" + 4 * current_iteration
- * to "value current_iteration"
- */
-
- uint32_t basereg = ROM32(bios->data[offset + 1]);
- uint32_t count = bios->data[offset + 5];
- int len = 6 + count * 4;
- int i;
-
- if (!iexec->execute)
- return len;
-
- BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
- offset, basereg, count);
-
- for (i = 0; i < count; i++) {
- uint32_t reg = basereg + i * 4;
- uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
-
- bios_wr32(bios, reg, data);
- }
-
- return len;
- }
-
- static int
- init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_SUB_DIRECT opcode: 0x5B ('[')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): subroutine offset (in bios)
- *
- * Calls a subroutine that will execute commands until INIT_DONE
- * is found.
- */
-
- uint16_t sub_offset = ROM16(bios->data[offset + 1]);
-
- if (!iexec->execute)
- return 3;
-
- BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
- offset, sub_offset);
-
- parse_init_table(bios, sub_offset, iexec);
-
- BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
-
- return 3;
- }
-
- static int
- init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_JUMP opcode: 0x5C ('\')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): offset (in bios)
- *
- * Continue execution of init table from 'offset'
- */
-
- uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
-
- if (!iexec->execute)
- return 3;
-
- BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
- return jmp_offset - offset;
- }
-
- static int
- init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_I2C_IF opcode: 0x5E ('^')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): DCB I2C table entry index
- * offset + 2 (8 bit): I2C slave address
- * offset + 3 (8 bit): I2C register
- * offset + 4 (8 bit): mask
- * offset + 5 (8 bit): data
- *
- * Read the register given by "I2C register" on the device addressed
- * by "I2C slave address" on the I2C bus given by "DCB I2C table
- * entry index". Compare the result AND "mask" to "data".
- * If they're not equal, skip subsequent opcodes until condition is
- * inverted (INIT_NOT), or we hit INIT_RESUME
- */
-
- uint8_t i2c_index = bios->data[offset + 1];
- uint8_t i2c_address = bios->data[offset + 2] >> 1;
- uint8_t reg = bios->data[offset + 3];
- uint8_t mask = bios->data[offset + 4];
- uint8_t data = bios->data[offset + 5];
- struct nouveau_i2c_chan *chan;
- union i2c_smbus_data val;
- int ret;
-
- /* no execute check by design */
-
- BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
- offset, i2c_index, i2c_address);
-
- chan = init_i2c_device_find(bios->dev, i2c_index);
- if (!chan)
- return -ENODEV;
-
- ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
- I2C_SMBUS_READ, reg,
- I2C_SMBUS_BYTE_DATA, &val);
- if (ret < 0) {
- BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
- "Mask: 0x%02X, Data: 0x%02X\n",
- offset, reg, mask, data);
- iexec->execute = 0;
- return 6;
- }
-
- BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
- "Mask: 0x%02X, Data: 0x%02X\n",
- offset, reg, val.byte, mask, data);
-
- iexec->execute = ((val.byte & mask) == data);
-
- return 6;
- }
-
- static int
- init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_COPY_NV_REG opcode: 0x5F ('_')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): src reg
- * offset + 5 (8 bit): shift
- * offset + 6 (32 bit): src mask
- * offset + 10 (32 bit): xor
- * offset + 14 (32 bit): dst reg
- * offset + 18 (32 bit): dst mask
- *
- * Shift REGVAL("src reg") right by (signed) "shift", AND result with
- * "src mask", then XOR with "xor". Write this OR'd with
- * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
- */
-
- uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
- uint8_t shift = bios->data[offset + 5];
- uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
- uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
- uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
- uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
- uint32_t srcvalue, dstvalue;
-
- if (!iexec->execute)
- return 22;
-
- BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
- "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
- offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
-
- srcvalue = bios_rd32(bios, srcreg);
-
- if (shift < 0x80)
- srcvalue >>= shift;
- else
- srcvalue <<= (0x100 - shift);
-
- srcvalue = (srcvalue & srcmask) ^ xor;
-
- dstvalue = bios_rd32(bios, dstreg) & dstmask;
-
- bios_wr32(bios, dstreg, dstvalue | srcvalue);
-
- return 22;
- }
-
- static int
- init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): CRTC port
- * offset + 3 (8 bit): CRTC index
- * offset + 4 (8 bit): data
- *
- * Write "data" to index "CRTC index" of "CRTC port"
- */
- uint16_t crtcport = ROM16(bios->data[offset + 1]);
- uint8_t crtcindex = bios->data[offset + 3];
- uint8_t data = bios->data[offset + 4];
-
- if (!iexec->execute)
- return 5;
-
- bios_idxprt_wr(bios, crtcport, crtcindex, data);
-
- return 5;
- }
-
- static inline void
- bios_md32(struct nvbios *bios, uint32_t reg,
- uint32_t mask, uint32_t val)
- {
- bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
- }
-
- static uint32_t
- peek_fb(struct drm_device *dev, struct io_mapping *fb,
- uint32_t off)
- {
- uint32_t val = 0;
-
- if (off < pci_resource_len(dev->pdev, 1)) {
- uint8_t __iomem *p =
- io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
-
- val = ioread32(p + (off & ~PAGE_MASK));
-
- io_mapping_unmap_atomic(p);
- }
-
- return val;
- }
-
- static void
- poke_fb(struct drm_device *dev, struct io_mapping *fb,
- uint32_t off, uint32_t val)
- {
- if (off < pci_resource_len(dev->pdev, 1)) {
- uint8_t __iomem *p =
- io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
-
- iowrite32(val, p + (off & ~PAGE_MASK));
- wmb();
-
- io_mapping_unmap_atomic(p);
- }
- }
-
- static inline bool
- read_back_fb(struct drm_device *dev, struct io_mapping *fb,
- uint32_t off, uint32_t val)
- {
- poke_fb(dev, fb, off, val);
- return val == peek_fb(dev, fb, off);
- }
-
- static int
- nv04_init_compute_mem(struct nvbios *bios)
- {
- struct drm_device *dev = bios->dev;
- uint32_t patt = 0xdeadbeef;
- struct io_mapping *fb;
- int i;
-
- /* Map the framebuffer aperture */
- fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
- pci_resource_len(dev->pdev, 1));
- if (!fb)
- return -ENOMEM;
-
- /* Sequencer and refresh off */
- NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
- bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
-
- bios_md32(bios, NV04_PFB_BOOT_0, ~0,
- NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
- NV04_PFB_BOOT_0_RAM_WIDTH_128 |
- NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
-
- for (i = 0; i < 4; i++)
- poke_fb(dev, fb, 4 * i, patt);
-
- poke_fb(dev, fb, 0x400000, patt + 1);
-
- if (peek_fb(dev, fb, 0) == patt + 1) {
- bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
- NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
- bios_md32(bios, NV04_PFB_DEBUG_0,
- NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
-
- for (i = 0; i < 4; i++)
- poke_fb(dev, fb, 4 * i, patt);
-
- if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
- bios_md32(bios, NV04_PFB_BOOT_0,
- NV04_PFB_BOOT_0_RAM_WIDTH_128 |
- NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-
- } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
- (patt & 0xffff0000)) {
- bios_md32(bios, NV04_PFB_BOOT_0,
- NV04_PFB_BOOT_0_RAM_WIDTH_128 |
- NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
-
- } else if (peek_fb(dev, fb, 0) != patt) {
- if (read_back_fb(dev, fb, 0x800000, patt))
- bios_md32(bios, NV04_PFB_BOOT_0,
- NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
- else
- bios_md32(bios, NV04_PFB_BOOT_0,
- NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
-
- bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
- NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
-
- } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
- bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-
- }
-
- /* Refresh on, sequencer on */
- bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
- NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
-
- io_mapping_free(fb);
- return 0;
- }
-
- static const uint8_t *
- nv05_memory_config(struct nvbios *bios)
- {
- /* Defaults for BIOSes lacking a memory config table */
- static const uint8_t default_config_tab[][2] = {
- { 0x24, 0x00 },
- { 0x28, 0x00 },
- { 0x24, 0x01 },
- { 0x1f, 0x00 },
- { 0x0f, 0x00 },
- { 0x17, 0x00 },
- { 0x06, 0x00 },
- { 0x00, 0x00 }
- };
- int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
- NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
-
- if (bios->legacy.mem_init_tbl_ptr)
- return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
- else
- return default_config_tab[i];
- }
-
- static int
- nv05_init_compute_mem(struct nvbios *bios)
- {
- struct drm_device *dev = bios->dev;
- const uint8_t *ramcfg = nv05_memory_config(bios);
- uint32_t patt = 0xdeadbeef;
- struct io_mapping *fb;
- int i, v;
-
- /* Map the framebuffer aperture */
- fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
- pci_resource_len(dev->pdev, 1));
- if (!fb)
- return -ENOMEM;
-
- /* Sequencer off */
- NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
-
- if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
- goto out;
-
- bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
-
- /* If present load the hardcoded scrambling table */
- if (bios->legacy.mem_init_tbl_ptr) {
- uint32_t *scramble_tab = (uint32_t *)&bios->data[
- bios->legacy.mem_init_tbl_ptr + 0x10];
-
- for (i = 0; i < 8; i++)
- bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
- ROM32(scramble_tab[i]));
- }
-
- /* Set memory type/width/length defaults depending on the straps */
- bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
-
- if (ramcfg[1] & 0x80)
- bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
-
- bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
- bios_md32(bios, NV04_PFB_CFG1, 0, 1);
-
- /* Probe memory bus width */
- for (i = 0; i < 4; i++)
- poke_fb(dev, fb, 4 * i, patt);
-
- if (peek_fb(dev, fb, 0xc) != patt)
- bios_md32(bios, NV04_PFB_BOOT_0,
- NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
-
- /* Probe memory length */
- v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
-
- if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
- (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
- !read_back_fb(dev, fb, 0, ++patt)))
- bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
-
- if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
- !read_back_fb(dev, fb, 0x800000, ++patt))
- bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
-
- if (!read_back_fb(dev, fb, 0x400000, ++patt))
- bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
- NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
-
- out:
- /* Sequencer on */
- NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
-
- io_mapping_free(fb);
- return 0;
- }
-
- static int
- nv10_init_compute_mem(struct nvbios *bios)
- {
- struct drm_device *dev = bios->dev;
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- const int mem_width[] = { 0x10, 0x00, 0x20 };
- const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
- uint32_t patt = 0xdeadbeef;
- struct io_mapping *fb;
- int i, j, k;
-
- /* Map the framebuffer aperture */
- fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
- pci_resource_len(dev->pdev, 1));
- if (!fb)
- return -ENOMEM;
-
- bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
-
- /* Probe memory bus width */
- for (i = 0; i < mem_width_count; i++) {
- bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
-
- for (j = 0; j < 4; j++) {
- for (k = 0; k < 4; k++)
- poke_fb(dev, fb, 0x1c, 0);
-
- poke_fb(dev, fb, 0x1c, patt);
- poke_fb(dev, fb, 0x3c, 0);
-
- if (peek_fb(dev, fb, 0x1c) == patt)
- goto mem_width_found;
- }
- }
-
- mem_width_found:
- patt <<= 1;
-
- /* Probe amount of installed memory */
- for (i = 0; i < 4; i++) {
- int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
-
- poke_fb(dev, fb, off, patt);
- poke_fb(dev, fb, 0, 0);
-
- peek_fb(dev, fb, 0);
- peek_fb(dev, fb, 0);
- peek_fb(dev, fb, 0);
- peek_fb(dev, fb, 0);
-
- if (peek_fb(dev, fb, off) == patt)
- goto amount_found;
- }
-
- /* IC missing - disable the upper half memory space. */
- bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
-
- amount_found:
- io_mapping_free(fb);
- return 0;
- }
-
- static int
- nv20_init_compute_mem(struct nvbios *bios)
- {
- struct drm_device *dev = bios->dev;
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
- uint32_t amount, off;
- struct io_mapping *fb;
-
- /* Map the framebuffer aperture */
- fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
- pci_resource_len(dev->pdev, 1));
- if (!fb)
- return -ENOMEM;
-
- bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
-
- /* Allow full addressing */
- bios_md32(bios, NV04_PFB_CFG0, 0, mask);
-
- amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
- for (off = amount; off > 0x2000000; off -= 0x2000000)
- poke_fb(dev, fb, off - 4, off);
-
- amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
- if (amount != peek_fb(dev, fb, amount - 4))
- /* IC missing - disable the upper half memory space. */
- bios_md32(bios, NV04_PFB_CFG0, mask, 0);
-
- io_mapping_free(fb);
- return 0;
- }
-
- static int
- init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_COMPUTE_MEM opcode: 0x63 ('c')
- *
- * offset (8 bit): opcode
- *
- * This opcode is meant to set the PFB memory config registers
- * appropriately so that we can correctly calculate how much VRAM it
- * has (on nv10 and better chipsets the amount of installed VRAM is
- * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
- *
- * The implementation of this opcode in general consists of several
- * parts:
- *
- * 1) Determination of memory type and density. Only necessary for
- * really old chipsets, the memory type reported by the strap bits
- * (0x101000) is assumed to be accurate on nv05 and newer.
- *
- * 2) Determination of the memory bus width. Usually done by a cunning
- * combination of writes to offsets 0x1c and 0x3c in the fb, and
- * seeing whether the written values are read back correctly.
- *
- * Only necessary on nv0x-nv1x and nv34, on the other cards we can
- * trust the straps.
- *
- * 3) Determination of how many of the card's RAM pads have ICs
- * attached, usually done by a cunning combination of writes to an
- * offset slightly less than the maximum memory reported by
- * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
- *
- * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
- * logs of the VBIOS and kmmio traces of the binary driver POSTing the
- * card show nothing being done for this opcode. Why is it still listed
- * in the table?!
- */
-
- /* no iexec->execute check by design */
-
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- int ret;
-
- if (dev_priv->chipset >= 0x40 ||
- dev_priv->chipset == 0x1a ||
- dev_priv->chipset == 0x1f)
- ret = 0;
- else if (dev_priv->chipset >= 0x20 &&
- dev_priv->chipset != 0x34)
- ret = nv20_init_compute_mem(bios);
- else if (dev_priv->chipset >= 0x10)
- ret = nv10_init_compute_mem(bios);
- else if (dev_priv->chipset >= 0x5)
- ret = nv05_init_compute_mem(bios);
- else
- ret = nv04_init_compute_mem(bios);
-
- if (ret)
- return ret;
-
- return 1;
- }
-
- static int
- init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_RESET opcode: 0x65 ('e')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (32 bit): value1
- * offset + 9 (32 bit): value2
- *
- * Assign "value1" to "register", then assign "value2" to "register"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint32_t value1 = ROM32(bios->data[offset + 5]);
- uint32_t value2 = ROM32(bios->data[offset + 9]);
- uint32_t pci_nv_19, pci_nv_20;
-
- /* no iexec->execute check by design */
-
- pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
- bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
-
- bios_wr32(bios, reg, value1);
-
- udelay(10);
-
- bios_wr32(bios, reg, value2);
- bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
-
- pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
- pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
- bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
-
- return 13;
- }
-
- static int
- init_configure_mem(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
- *
- * offset (8 bit): opcode
- *
- * Equivalent to INIT_DONE on bios version 3 or greater.
- * For early bios versions, sets up the memory registers, using values
- * taken from the memory init table
- */
-
- /* no iexec->execute check by design */
-
- uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
- uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
- uint32_t reg, data;
-
- if (bios->major_version > 2)
- return 0;
-
- bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
- bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
-
- if (bios->data[meminitoffs] & 1)
- seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
-
- for (reg = ROM32(bios->data[seqtbloffs]);
- reg != 0xffffffff;
- reg = ROM32(bios->data[seqtbloffs += 4])) {
-
- switch (reg) {
- case NV04_PFB_PRE:
- data = NV04_PFB_PRE_CMD_PRECHARGE;
- break;
- case NV04_PFB_PAD:
- data = NV04_PFB_PAD_CKE_NORMAL;
- break;
- case NV04_PFB_REF:
- data = NV04_PFB_REF_CMD_REFRESH;
- break;
- default:
- data = ROM32(bios->data[meminitdata]);
- meminitdata += 4;
- if (data == 0xffffffff)
- continue;
- }
-
- bios_wr32(bios, reg, data);
- }
-
- return 1;
- }
-
- static int
- init_configure_clk(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
- *
- * offset (8 bit): opcode
- *
- * Equivalent to INIT_DONE on bios version 3 or greater.
- * For early bios versions, sets up the NVClk and MClk PLLs, using
- * values taken from the memory init table
- */
-
- /* no iexec->execute check by design */
-
- uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
- int clock;
-
- if (bios->major_version > 2)
- return 0;
-
- clock = ROM16(bios->data[meminitoffs + 4]) * 10;
- setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
-
- clock = ROM16(bios->data[meminitoffs + 2]) * 10;
- if (bios->data[meminitoffs] & 1) /* DDR */
- clock *= 2;
- setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
-
- return 1;
- }
-
- static int
- init_configure_preinit(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
- *
- * offset (8 bit): opcode
- *
- * Equivalent to INIT_DONE on bios version 3 or greater.
- * For early bios versions, does early init, loading ram and crystal
- * configuration from straps into CR3C
- */
-
- /* no iexec->execute check by design */
-
- uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
- uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
-
- if (bios->major_version > 2)
- return 0;
-
- bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
- NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
-
- return 1;
- }
-
- static int
- init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_IO opcode: 0x69 ('i')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): CRTC port
- * offset + 3 (8 bit): mask
- * offset + 4 (8 bit): data
- *
- * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
- */
-
- struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
- uint16_t crtcport = ROM16(bios->data[offset + 1]);
- uint8_t mask = bios->data[offset + 3];
- uint8_t data = bios->data[offset + 4];
-
- if (!iexec->execute)
- return 5;
-
- BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
- offset, crtcport, mask, data);
-
- /*
- * I have no idea what this does, but NVIDIA do this magic sequence
- * in the places where this INIT_IO happens..
- */
- if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
- int i;
-
- bios_wr32(bios, 0x614100, (bios_rd32(
- bios, 0x614100) & 0x0fffffff) | 0x00800000);
-
- bios_wr32(bios, 0x00e18c, bios_rd32(
- bios, 0x00e18c) | 0x00020000);
-
- bios_wr32(bios, 0x614900, (bios_rd32(
- bios, 0x614900) & 0x0fffffff) | 0x00800000);
-
- bios_wr32(bios, 0x000200, bios_rd32(
- bios, 0x000200) & ~0x40000000);
-
- mdelay(10);
-
- bios_wr32(bios, 0x00e18c, bios_rd32(
- bios, 0x00e18c) & ~0x00020000);
-
- bios_wr32(bios, 0x000200, bios_rd32(
- bios, 0x000200) | 0x40000000);
-
- bios_wr32(bios, 0x614100, 0x00800018);
- bios_wr32(bios, 0x614900, 0x00800018);
-
- mdelay(10);
-
- bios_wr32(bios, 0x614100, 0x10000018);
- bios_wr32(bios, 0x614900, 0x10000018);
-
- for (i = 0; i < 3; i++)
- bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
- bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
-
- for (i = 0; i < 2; i++)
- bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
- bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
-
- for (i = 0; i < 3; i++)
- bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
- bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
-
- for (i = 0; i < 2; i++)
- bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
- bios, 0x614200 + (i*0x800)) & 0xfffffff0);
-
- for (i = 0; i < 2; i++)
- bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
- bios, 0x614108 + (i*0x800)) & 0x0fffffff);
- return 5;
- }
-
- bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
- data);
- return 5;
- }
-
- static int
- init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_SUB opcode: 0x6B ('k')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): script number
- *
- * Execute script number "script number", as a subroutine
- */
-
- uint8_t sub = bios->data[offset + 1];
-
- if (!iexec->execute)
- return 2;
-
- BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
-
- parse_init_table(bios,
- ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
- iexec);
-
- BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
-
- return 2;
- }
-
- static int
- init_ram_condition(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_RAM_CONDITION opcode: 0x6D ('m')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): mask
- * offset + 2 (8 bit): cmpval
- *
- * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
- * If condition not met skip subsequent opcodes until condition is
- * inverted (INIT_NOT), or we hit INIT_RESUME
- */
-
- uint8_t mask = bios->data[offset + 1];
- uint8_t cmpval = bios->data[offset + 2];
- uint8_t data;
-
- if (!iexec->execute)
- return 3;
-
- data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
-
- BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
- offset, data, cmpval);
-
- if (data == cmpval)
- BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
- else {
- BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
- iexec->execute = false;
- }
-
- return 3;
- }
-
- static int
- init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_NV_REG opcode: 0x6E ('n')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (32 bit): mask
- * offset + 9 (32 bit): data
- *
- * Assign ((REGVAL("register") & "mask") | "data") to "register"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint32_t mask = ROM32(bios->data[offset + 5]);
- uint32_t data = ROM32(bios->data[offset + 9]);
-
- if (!iexec->execute)
- return 13;
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
- offset, reg, mask, data);
-
- bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
-
- return 13;
- }
-
- static int
- init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_MACRO opcode: 0x6F ('o')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): macro number
- *
- * Look up macro index "macro number" in the macro index table.
- * The macro index table entry has 1 byte for the index in the macro
- * table, and 1 byte for the number of times to repeat the macro.
- * The macro table entry has 4 bytes for the register address and
- * 4 bytes for the value to write to that register
- */
-
- uint8_t macro_index_tbl_idx = bios->data[offset + 1];
- uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
- uint8_t macro_tbl_idx = bios->data[tmp];
- uint8_t count = bios->data[tmp + 1];
- uint32_t reg, data;
- int i;
-
- if (!iexec->execute)
- return 2;
-
- BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
- "Count: 0x%02X\n",
- offset, macro_index_tbl_idx, macro_tbl_idx, count);
-
- for (i = 0; i < count; i++) {
- uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
-
- reg = ROM32(bios->data[macroentryptr]);
- data = ROM32(bios->data[macroentryptr + 4]);
-
- bios_wr32(bios, reg, data);
- }
-
- return 2;
- }
-
- static int
- init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_DONE opcode: 0x71 ('q')
- *
- * offset (8 bit): opcode
- *
- * End the current script
- */
-
- /* mild retval abuse to stop parsing this table */
- return 0;
- }
-
- static int
- init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_RESUME opcode: 0x72 ('r')
- *
- * offset (8 bit): opcode
- *
- * End the current execute / no-execute condition
- */
-
- if (iexec->execute)
- return 1;
-
- iexec->execute = true;
- BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
-
- return 1;
- }
-
- static int
- init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_TIME opcode: 0x74 ('t')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): time
- *
- * Sleep for "time" microseconds.
- */
-
- unsigned time = ROM16(bios->data[offset + 1]);
-
- if (!iexec->execute)
- return 3;
-
- BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
- offset, time);
-
- if (time < 1000)
- udelay(time);
- else
- mdelay((time + 900) / 1000);
-
- return 3;
- }
-
- static int
- init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_CONDITION opcode: 0x75 ('u')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): condition number
- *
- * Check condition "condition number" in the condition table.
- * If condition not met skip subsequent opcodes until condition is
- * inverted (INIT_NOT), or we hit INIT_RESUME
- */
-
- uint8_t cond = bios->data[offset + 1];
-
- if (!iexec->execute)
- return 2;
-
- BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
-
- if (bios_condition_met(bios, offset, cond))
- BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
- else {
- BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
- iexec->execute = false;
- }
-
- return 2;
- }
-
- static int
- init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_IO_CONDITION opcode: 0x76
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): condition number
- *
- * Check condition "condition number" in the io condition table.
- * If condition not met skip subsequent opcodes until condition is
- * inverted (INIT_NOT), or we hit INIT_RESUME
- */
-
- uint8_t cond = bios->data[offset + 1];
-
- if (!iexec->execute)
- return 2;
-
- BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
-
- if (io_condition_met(bios, offset, cond))
- BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
- else {
- BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
- iexec->execute = false;
- }
-
- return 2;
- }
-
- static int
- init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_INDEX_IO opcode: 0x78 ('x')
- *
- * offset (8 bit): opcode
- * offset + 1 (16 bit): CRTC port
- * offset + 3 (8 bit): CRTC index
- * offset + 4 (8 bit): mask
- * offset + 5 (8 bit): data
- *
- * Read value at index "CRTC index" on "CRTC port", AND with "mask",
- * OR with "data", write-back
- */
-
- uint16_t crtcport = ROM16(bios->data[offset + 1]);
- uint8_t crtcindex = bios->data[offset + 3];
- uint8_t mask = bios->data[offset + 4];
- uint8_t data = bios->data[offset + 5];
- uint8_t value;
-
- if (!iexec->execute)
- return 6;
-
- BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
- "Data: 0x%02X\n",
- offset, crtcport, crtcindex, mask, data);
-
- value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
- bios_idxprt_wr(bios, crtcport, crtcindex, value);
-
- return 6;
- }
-
- static int
- init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_PLL opcode: 0x79 ('y')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (16 bit): freq
- *
- * Set PLL register "register" to coefficients for frequency (10kHz)
- * "freq"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint16_t freq = ROM16(bios->data[offset + 5]);
-
- if (!iexec->execute)
- return 7;
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
-
- setPLL(bios, reg, freq * 10);
-
- return 7;
- }
-
- static int
- init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_REG opcode: 0x7A ('z')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (32 bit): value
- *
- * Assign "value" to "register"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint32_t value = ROM32(bios->data[offset + 5]);
-
- if (!iexec->execute)
- return 9;
-
- if (reg == 0x000200)
- value |= 1;
-
- bios_wr32(bios, reg, value);
-
- return 9;
- }
-
- static int
- init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): PLL type
- * offset + 2 (32 bit): frequency 0
- *
- * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
- * ram_restrict_table_ptr. The value read from there is used to select
- * a frequency from the table starting at 'frequency 0' to be
- * programmed into the PLL corresponding to 'type'.
- *
- * The PLL limits table on cards using this opcode has a mapping of
- * 'type' to the relevant registers.
- */
-
- struct drm_device *dev = bios->dev;
- uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
- uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
- uint8_t type = bios->data[offset + 1];
- uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
- uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
- int len = 2 + bios->ram_restrict_group_count * 4;
- int i;
-
- if (!iexec->execute)
- return len;
-
- if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
- NV_ERROR(dev, "PLL limits table not version 3.x\n");
- return len; /* deliberate, allow default clocks to remain */
- }
-
- entry = pll_limits + pll_limits[1];
- for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
- if (entry[0] == type) {
- uint32_t reg = ROM32(entry[3]);
-
- BIOSLOG(bios, "0x%04X: "
- "Type %02x Reg 0x%08x Freq %dKHz\n",
- offset, type, reg, freq);
-
- setPLL(bios, reg, freq);
- return len;
- }
- }
-
- NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
- return len;
- }
-
- static int
- init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_8C opcode: 0x8C ('')
- *
- * NOP so far....
- *
- */
-
- return 1;
- }
-
- static int
- init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_8D opcode: 0x8D ('')
- *
- * NOP so far....
- *
- */
-
- return 1;
- }
-
- static int
- init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_GPIO opcode: 0x8E ('')
- *
- * offset (8 bit): opcode
- *
- * Loop over all entries in the DCB GPIO table, and initialise
- * each GPIO according to various values listed in each entry
- */
-
- if (iexec->execute && bios->execute)
- nouveau_gpio_reset(bios->dev);
-
- return 1;
- }
-
- static int
- init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): reg
- * offset + 5 (8 bit): regincrement
- * offset + 6 (8 bit): count
- * offset + 7 (32 bit): value 1,1
- * ...
- *
- * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
- * ram_restrict_table_ptr. The value read from here is 'n', and
- * "value 1,n" gets written to "reg". This repeats "count" times and on
- * each iteration 'm', "reg" increases by "regincrement" and
- * "value m,n" is used. The extent of n is limited by a number read
- * from the 'M' BIT table, herein called "blocklen"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint8_t regincrement = bios->data[offset + 5];
- uint8_t count = bios->data[offset + 6];
- uint32_t strap_ramcfg, data;
- /* previously set by 'M' BIT table */
- uint16_t blocklen = bios->ram_restrict_group_count * 4;
- int len = 7 + count * blocklen;
- uint8_t index;
- int i;
-
- /* critical! to know the length of the opcode */;
- if (!blocklen) {
- NV_ERROR(bios->dev,
- "0x%04X: Zero block length - has the M table "
- "been parsed?\n", offset);
- return -EINVAL;
- }
-
- if (!iexec->execute)
- return len;
-
- strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
- index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
-
- BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
- "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
- offset, reg, regincrement, count, strap_ramcfg, index);
-
- for (i = 0; i < count; i++) {
- data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
-
- bios_wr32(bios, reg, data);
-
- reg += regincrement;
- }
-
- return len;
- }
-
- static int
- init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_COPY_ZM_REG opcode: 0x90 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): src reg
- * offset + 5 (32 bit): dst reg
- *
- * Put contents of "src reg" into "dst reg"
- */
-
- uint32_t srcreg = ROM32(bios->data[offset + 1]);
- uint32_t dstreg = ROM32(bios->data[offset + 5]);
-
- if (!iexec->execute)
- return 9;
-
- bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
-
- return 9;
- }
-
- static int
- init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
- struct init_exec *iexec)
- {
- /*
- * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): dst reg
- * offset + 5 (8 bit): count
- * offset + 6 (32 bit): data 1
- * ...
- *
- * For each of "count" values write "data n" to "dst reg"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint8_t count = bios->data[offset + 5];
- int len = 6 + count * 4;
- int i;
-
- if (!iexec->execute)
- return len;
-
- for (i = 0; i < count; i++) {
- uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
- bios_wr32(bios, reg, data);
- }
-
- return len;
- }
-
- static int
- init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_RESERVED opcode: 0x92 ('')
- *
- * offset (8 bit): opcode
- *
- * Seemingly does nothing
- */
-
- return 1;
- }
-
- static int
- init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_96 opcode: 0x96 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): sreg
- * offset + 5 (8 bit): sshift
- * offset + 6 (8 bit): smask
- * offset + 7 (8 bit): index
- * offset + 8 (32 bit): reg
- * offset + 12 (32 bit): mask
- * offset + 16 (8 bit): shift
- *
- */
-
- uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
- uint32_t reg = ROM32(bios->data[offset + 8]);
- uint32_t mask = ROM32(bios->data[offset + 12]);
- uint32_t val;
-
- val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
- if (bios->data[offset + 5] < 0x80)
- val >>= bios->data[offset + 5];
- else
- val <<= (0x100 - bios->data[offset + 5]);
- val &= bios->data[offset + 6];
-
- val = bios->data[ROM16(bios->data[xlatptr]) + val];
- val <<= bios->data[offset + 16];
-
- if (!iexec->execute)
- return 17;
-
- bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
- return 17;
- }
-
- static int
- init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_97 opcode: 0x97 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): register
- * offset + 5 (32 bit): mask
- * offset + 9 (32 bit): value
- *
- * Adds "value" to "register" preserving the fields specified
- * by "mask"
- */
-
- uint32_t reg = ROM32(bios->data[offset + 1]);
- uint32_t mask = ROM32(bios->data[offset + 5]);
- uint32_t add = ROM32(bios->data[offset + 9]);
- uint32_t val;
-
- val = bios_rd32(bios, reg);
- val = (val & mask) | ((val + add) & ~mask);
-
- if (!iexec->execute)
- return 13;
-
- bios_wr32(bios, reg, val);
- return 13;
- }
+ #include <subdev/bios.h>
- static int
- init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_AUXCH opcode: 0x98 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): address
- * offset + 5 (8 bit): count
- * offset + 6 (8 bit): mask 0
- * offset + 7 (8 bit): data 0
- * ...
- *
- */
-
- struct drm_device *dev = bios->dev;
- struct nouveau_i2c_chan *auxch;
- uint32_t addr = ROM32(bios->data[offset + 1]);
- uint8_t count = bios->data[offset + 5];
- int len = 6 + count * 2;
- int ret, i;
-
- if (!bios->display.output) {
- NV_ERROR(dev, "INIT_AUXCH: no active output\n");
- return len;
- }
-
- auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
- if (!auxch) {
- NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
- bios->display.output->i2c_index);
- return len;
- }
-
- if (!iexec->execute)
- return len;
-
- offset += 6;
- for (i = 0; i < count; i++, offset += 2) {
- uint8_t data;
-
- ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
- if (ret) {
- NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
- return len;
- }
-
- data &= bios->data[offset + 0];
- data |= bios->data[offset + 1];
-
- ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
- if (ret) {
- NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
- return len;
- }
- }
-
- return len;
- }
-
- static int
- init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_ZM_AUXCH opcode: 0x99 ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (32 bit): address
- * offset + 5 (8 bit): count
- * offset + 6 (8 bit): data 0
- * ...
- *
- */
-
- struct drm_device *dev = bios->dev;
- struct nouveau_i2c_chan *auxch;
- uint32_t addr = ROM32(bios->data[offset + 1]);
- uint8_t count = bios->data[offset + 5];
- int len = 6 + count;
- int ret, i;
-
- if (!bios->display.output) {
- NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
- return len;
- }
-
- auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
- if (!auxch) {
- NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
- bios->display.output->i2c_index);
- return len;
- }
-
- if (!iexec->execute)
- return len;
-
- offset += 6;
- for (i = 0; i < count; i++, offset++) {
- ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
- if (ret) {
- NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
- return len;
- }
- }
-
- return len;
- }
-
- static int
- init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
- {
- /*
- * INIT_I2C_LONG_IF opcode: 0x9A ('')
- *
- * offset (8 bit): opcode
- * offset + 1 (8 bit): DCB I2C table entry index
- * offset + 2 (8 bit): I2C slave address
- * offset + 3 (16 bit): I2C register
- * offset + 5 (8 bit): mask
- * offset + 6 (8 bit): data
- *
- * Read the register given by "I2C register" on the device addressed
- * by "I2C slave address" on the I2C bus given by "DCB I2C table
- * entry index". Compare the result AND "mask" to "data".
- * If they're not equal, skip subsequent opcodes until condition is
- * inverted (INIT_NOT), or we hit INIT_RESUME
- */
-
- uint8_t i2c_index = bios->data[offset + 1];
- uint8_t i2c_address = bios->data[offset + 2] >> 1;
- uint8_t reglo = bios->data[offset + 3];
- uint8_t reghi = bios->data[offset + 4];
- uint8_t mask = bios->data[offset + 5];
- uint8_t data = bios->data[offset + 6];
- struct nouveau_i2c_chan *chan;
- uint8_t buf0[2] = { reghi, reglo };
- uint8_t buf1[1];
- struct i2c_msg msg[2] = {
- { i2c_address, 0, 1, buf0 },
- { i2c_address, I2C_M_RD, 1, buf1 },
- };
- int ret;
-
- /* no execute check by design */
-
- BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
- offset, i2c_index, i2c_address);
-
- chan = init_i2c_device_find(bios->dev, i2c_index);
- if (!chan)
- return -ENODEV;
-#include "drmP.h"
++#include <drm/drmP.h>
+
+ #include "nouveau_drm.h"
+ #include "nouveau_reg.h"
+ #include "nouveau_hw.h"
+ #include "nouveau_encoder.h"
- ret = i2c_transfer(&chan->adapter, msg, 2);
- if (ret < 0) {
- BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
- "Mask: 0x%02X, Data: 0x%02X\n",
- offset, reghi, reglo, mask, data);
- iexec->execute = 0;
- return 7;
- }
+ #include <linux/io-mapping.h>
+ #include <linux/firmware.h>
- BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
- "Mask: 0x%02X, Data: 0x%02X\n",
- offset, reghi, reglo, buf1[0], mask, data);
+ /* these defines are made up */
+ #define NV_CIO_CRE_44_HEADA 0x0
+ #define NV_CIO_CRE_44_HEADB 0x3
+ #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
- iexec->execute = ((buf1[0] & mask) == data);
+ #define EDID1_LEN 128
- return 7;
- }
+ #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
+ #define LOG_OLD_VALUE(x)
- static struct init_tbl_entry itbl_entry[] = {
- /* command name , id , length , offset , mult , command handler */
- /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
- { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
- { "INIT_REPEAT" , 0x33, init_repeat },
- { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
- { "INIT_END_REPEAT" , 0x36, init_end_repeat },
- { "INIT_COPY" , 0x37, init_copy },
- { "INIT_NOT" , 0x38, init_not },
- { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
- { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
- { "INIT_OP_3B" , 0x3B, init_op_3b },
- { "INIT_OP_3C" , 0x3C, init_op_3c },
- { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
- { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
- { "INIT_PLL2" , 0x4B, init_pll2 },
- { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
- { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
- { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
- { "INIT_TMDS" , 0x4F, init_tmds },
- { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
- { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
- { "INIT_CR" , 0x52, init_cr },
- { "INIT_ZM_CR" , 0x53, init_zm_cr },
- { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
- { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
- { "INIT_LTIME" , 0x57, init_ltime },
- { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
- /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
- { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
- { "INIT_JUMP" , 0x5C, init_jump },
- { "INIT_I2C_IF" , 0x5E, init_i2c_if },
- { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
- { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
- { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
- { "INIT_RESET" , 0x65, init_reset },
- { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
- { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
- { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
- { "INIT_IO" , 0x69, init_io },
- { "INIT_SUB" , 0x6B, init_sub },
- { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
- { "INIT_NV_REG" , 0x6E, init_nv_reg },
- { "INIT_MACRO" , 0x6F, init_macro },
- { "INIT_DONE" , 0x71, init_done },
- { "INIT_RESUME" , 0x72, init_resume },
- /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
- { "INIT_TIME" , 0x74, init_time },
- { "INIT_CONDITION" , 0x75, init_condition },
- { "INIT_IO_CONDITION" , 0x76, init_io_condition },
- { "INIT_INDEX_IO" , 0x78, init_index_io },
- { "INIT_PLL" , 0x79, init_pll },
- { "INIT_ZM_REG" , 0x7A, init_zm_reg },
- { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
- { "INIT_8C" , 0x8C, init_8c },
- { "INIT_8D" , 0x8D, init_8d },
- { "INIT_GPIO" , 0x8E, init_gpio },
- { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
- { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
- { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
- { "INIT_RESERVED" , 0x92, init_reserved },
- { "INIT_96" , 0x96, init_96 },
- { "INIT_97" , 0x97, init_97 },
- { "INIT_AUXCH" , 0x98, init_auxch },
- { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
- { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
- { NULL , 0 , NULL }
+ struct init_exec {
+ bool execute;
+ bool repeat;
};
- #define MAX_TABLE_OPS 1000
-
- static int
- parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
+ static bool nv_cksum(const uint8_t *data, unsigned int length)
{
/*
- * Parses all commands in an init table.
- *
- * We start out executing all commands found in the init table. Some
- * opcodes may change the status of iexec->execute to SKIP, which will
- * cause the following opcodes to perform no operation until the value
- * is changed back to EXECUTE.
- */
-
- int count = 0, i, ret;
- uint8_t id;
-
- /* catch NULL script pointers */
- if (offset == 0)
- return 0;
-
- /*
- * Loop until INIT_DONE causes us to break out of the loop
- * (or until offset > bios length just in case... )
- * (and no more than MAX_TABLE_OPS iterations, just in case... )
+ * There's a few checksums in the BIOS, so here's a generic checking
+ * function.
*/
- while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
- id = bios->data[offset];
-
- /* Find matching id in itbl_entry */
- for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
- ;
-
- if (!itbl_entry[i].name) {
- NV_ERROR(bios->dev,
- "0x%04X: Init table command not found: "
- "0x%02X\n", offset, id);
- return -ENOENT;
- }
-
- BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
- itbl_entry[i].id, itbl_entry[i].name);
-
- /* execute eventual command handler */
- ret = (*itbl_entry[i].handler)(bios, offset, iexec);
- if (ret < 0) {
- NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
- "table opcode: %s %d\n", offset,
- itbl_entry[i].name, ret);
- }
-
- if (ret <= 0)
- break;
-
- /*
- * Add the offset of the current command including all data
- * of that command. The offset will then be pointing on the
- * next op code.
- */
- offset += ret;
- }
-
- if (offset >= bios->length)
- NV_WARN(bios->dev,
- "Offset 0x%04X greater than known bios image length. "
- "Corrupt image?\n", offset);
- if (count >= MAX_TABLE_OPS)
- NV_WARN(bios->dev,
- "More than %d opcodes to a table is unlikely, "
- "is the bios image corrupt?\n", MAX_TABLE_OPS);
-
- return 0;
- }
-
- static void
- parse_init_tables(struct nvbios *bios)
- {
- /* Loops and calls parse_init_table() for each present table. */
-
- int i = 0;
- uint16_t table;
- struct init_exec iexec = {true, false};
-
- if (bios->old_style_init) {
- if (bios->init_script_tbls_ptr)
- parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
- if (bios->extra_init_script_tbl_ptr)
- parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
+ int i;
+ uint8_t sum = 0;
- return;
- }
+ for (i = 0; i < length; i++)
+ sum += data[i];
- while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
- NV_INFO(bios->dev,
- "Parsing VBIOS init table %d at offset 0x%04X\n",
- i / 2, table);
- BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
+ if (sum)
+ return true;
- parse_init_table(bios, table, &iexec);
- i += 2;
- }
+ return false;
}
static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
projects / users / willy / pagecache.git / commitdiff