media: drivers: media: pci: cx18: Couple of spell fixes in the file cx18-av-core.c

s/minimze/minimize/
s/initallize/initialize/

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/media/pci/cx18/cx18-av-core.c b/drivers/media/pci/cx18/cx18-av-core.c
index b33eb08631b1e8d12be91c838f076653b1bdaad1..11cfe35fd730b1ed3b1f5e542ae5ced6af680045 100644 (file)
--- a/drivers/media/pci/cx18/cx18-av-core.c
+++ b/drivers/media/pci/cx18/cx18-av-core.c
@@ -89,7 +89,7 @@ static void cx18_av_init(struct cx18 *cx)
        /*
         * The crystal freq used in calculations in this driver will be
         * 28.636360 MHz.
-        * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
+        * Aim to run the PLLs' VCOs near 400 MHz to minimize errors.
         */
 
        /*
@@ -122,7 +122,7 @@ static void cx18_av_initialize(struct v4l2_subdev *sd)
        cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
                                                 0x03000000, 0x13000000);
 
-       /* initallize the PLL by toggling sleep bit */
+       /* initialize the PLL by toggling sleep bit */
        v = cx18_av_read4(cx, CXADEC_HOST_REG1);
        /* enable sleep mode - register appears to be read only... */
        cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);