#include "sdhci-pltfm.h"
 #include "sdhci-esdhc.h"
 
-#define        SDHCI_CTRL_D3CD                 0x08
+#define        ESDHC_CTRL_D3CD                 0x08
 /* VENDOR SPEC register */
-#define SDHCI_VENDOR_SPEC              0xC0
-#define  SDHCI_VENDOR_SPEC_SDIO_QUIRK  0x00000002
-#define SDHCI_WTMK_LVL                 0x44
-#define SDHCI_MIX_CTRL                 0x48
+#define ESDHC_VENDOR_SPEC              0xc0
+#define  ESDHC_VENDOR_SPEC_SDIO_QUIRK  (1 << 1)
+#define ESDHC_WTMK_LVL                 0x44
+#define ESDHC_MIX_CTRL                 0x48
 
 /*
  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  * Define this macro DMA error INT for fsl eSDHC
  */
-#define SDHCI_INT_VENDOR_SPEC_DMA_ERR  0x10000000
+#define ESDHC_INT_VENDOR_SPEC_DMA_ERR  (1 << 28)
 
 /*
  * The CMDTYPE of the CMD register (offset 0xE) should be set to
        }
 
        if (unlikely(reg == SDHCI_INT_STATUS)) {
-               if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
-                       val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
+               if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
+                       val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
                        val |= SDHCI_INT_ADMA_ERROR;
                }
        }
                         * re-sample it by the following steps.
                         */
                        data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
-                       data &= ~SDHCI_CTRL_D3CD;
+                       data &= ~ESDHC_CTRL_D3CD;
                        writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
-                       data |= SDHCI_CTRL_D3CD;
+                       data |= ESDHC_CTRL_D3CD;
                        writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
                }
        }
                                && (reg == SDHCI_INT_STATUS)
                                && (val & SDHCI_INT_DATA_END))) {
                        u32 v;
-                       v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
-                       v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
-                       writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
+                       v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
+                       v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
+                       writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
        }
 
        if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
                if (val & SDHCI_INT_ADMA_ERROR) {
                        val &= ~SDHCI_INT_ADMA_ERROR;
-                       val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
+                       val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
                }
        }
 
                                && (host->cmd->data->blocks > 1)
                                && (host->cmd->data->flags & MMC_DATA_READ)) {
                        u32 v;
-                       v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
-                       v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
-                       writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
+                       v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
+                       v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
+                       writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
                }
                imx_data->scratchpad = val;
                return;
                        val |= SDHCI_CMD_ABORTCMD;
 
                if (is_imx6q_usdhc(imx_data)) {
-                       u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL);
+                       u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
                        m = imx_data->scratchpad | (m & 0xffff0000);
-                       writel(m, host->ioaddr + SDHCI_MIX_CTRL);
+                       writel(m, host->ioaddr + ESDHC_MIX_CTRL);
                        writel(val << 16,
                               host->ioaddr + SDHCI_TRANSFER_MODE);
                } else {
         * to something insane.  Change it back here.
         */
        if (is_imx6q_usdhc(imx_data))
-               writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL);
+               writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
 
        boarddata = &imx_data->boarddata;
        if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {