]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
drm/amd/amdgpu: update GFX12 wave data registers
authorTom St Denis <tom.stdenis@amd.com>
Thu, 24 Aug 2023 13:23:04 +0000 (09:23 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 2 May 2024 20:18:11 +0000 (16:18 -0400)
Update the registers for gfx12.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

index 68a66ccb0100dc54f98cccae1c013c4cd753dd9e..730d57a10077f0dcf6dff59f257ec300ca0fa141 100644 (file)
@@ -659,8 +659,8 @@ static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
         * zero here */
        WARN_ON(simd != 0);
 
-       /* type 3 wave data */
-       dst[(*no_fields)++] = 3;
+       /* type 4 wave data */
+       dst[(*no_fields)++] = 4;
        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
@@ -675,6 +675,15 @@ static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
        dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);
 }
 
 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,