#define NVA06F_V0_ENGINE_MSPDEC                                      0x00000020
 #define NVA06F_V0_ENGINE_MSPPP                                       0x00000040
 #define NVA06F_V0_ENGINE_MSENC                                       0x00000080
+#define NVA06F_V0_ENGINE_NVDEC                                       0x00000200
 #define NVA06F_V0_ENGINE_NVENC0                                      0x00000400
 #define NVA06F_V0_ENGINE_NVENC1                                      0x00000800
 #define NVA06F_V0_ENGINE_CE0                                         0x00010000
 
                case 0x0000000d: engidx = NVKM_ENGINE_SEC; break;
                case 0x0000000e: engidx = NVKM_ENGINE_NVENC0; break;
                case 0x0000000f: engidx = NVKM_ENGINE_NVENC1; break;
+               case 0x00000010: engidx = NVKM_ENGINE_NVDEC; break;
                        break;
                default:
                        break;
 
        case NVKM_ENGINE_MSPPP : return 0x0260;
        case NVKM_ENGINE_MSVLD : return 0x0270;
        case NVKM_ENGINE_MSENC : return 0x0290;
+       case NVKM_ENGINE_NVDEC : return 0x02100270;
        case NVKM_ENGINE_NVENC0: return 0x02100290;
        case NVKM_ENGINE_NVENC1: return 0x0210;
        default:
        { NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
        { NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
        { NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
+       { NVA06F_V0_ENGINE_NVDEC , BIT_ULL(NVKM_ENGINE_NVDEC ) },
        { NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
        { NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
        { NVA06F_V0_ENGINE_CE0   , BIT_ULL(NVKM_ENGINE_CE0   ) },