work->base = base;
 
-       r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
+       r = drm_crtc_vblank_get(crtc);
        if (r) {
                DRM_ERROR("failed to get vblank before flip\n");
                goto pflip_cleanup;
        return 0;
 
 vblank_cleanup:
-       drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
+       drm_crtc_vblank_put(&amdgpu_crtc->base);
 
 pflip_cleanup:
        if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
 
 
        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
-       drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
+       drm_crtc_vblank_put(&amdgpu_crtc->base);
        schedule_work(&works->unpin_work);
 
        return 0;
 
 
        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
-       drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
+       drm_crtc_vblank_put(&amdgpu_crtc->base);
        schedule_work(&works->unpin_work);
 
        return 0;
 
 
        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
-       drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
+       drm_crtc_vblank_put(&amdgpu_crtc->base);
        schedule_work(&works->unpin_work);
 
        return 0;