drm/i915: add config function for YCBCR420 outputs

This patch checks encoder level support for YCBCR420 outputs.
The logic goes as simple as this:
If the input mode is YCBCR420-only mode: prepare HDMI for
YCBCR420 output, else continue with RGB output mode.

It checks if the mode is YCBCR420 and source can support this
output then it marks the ycbcr_420 output indicator into crtc
state, for further staging in driver.

V2: Split the patch into two, kept helper functions in DRM layer.
V3: Changed the compute_config function based on new DRM API.
V4: Rebase
V5: Rebase
V6: Check and handle YCBCR420-only modes, discard the property
    based approach (Ville)
V7: Addressed review comments from Ville
    - add else case in 12BPC check.
    - extract ycbcr420 state inside hdmi_12bpc_possible function.
V8: Addressed review comments from Ville
    - Remove extra blank lines.
    - Remove "HDMI" from the description of ycbcr420 state variable.
    - Remove local variable, use crtc_state->ycbcr420 instead.
    Added r-b from Ville.
V9: Rebase
V10: Added r-b from Imre

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500650709-14447-2-git-send-email-shashank.sharma@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6c823cc02db3d82d15a8dcabc80ecbde68bc0464..6908d3b4218a3a0a15be02e6cdd9588ff3223152 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10969,6 +10969,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
        PIPE_CONF_CHECK_I(hdmi_scrambling);
        PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
        PIPE_CONF_CHECK_I(has_infoframe);
+       PIPE_CONF_CHECK_I(ycbcr420);
 
        PIPE_CONF_CHECK_I(has_audio);
 

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9c135f7a28682f1439822cf98a25d22b8bea0341..ee0daecff7136a5c7e5db46ce8d640c81988ff63 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -780,6 +780,9 @@ struct intel_crtc_state {
 
        /* HDMI High TMDS char rate ratio */
        bool hdmi_high_tmds_clock_ratio;
+
+       /* output format is YCBCR 4:2:0 */
+       bool ycbcr420;
 };
 
 struct intel_crtc {

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2f831cfdd24330050bdfc4f6645b9a419280b77c..0b63b9fcbcc10a900b68058d0b60f0dad4f60a05 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1330,8 +1330,15 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
                if (connector_state->crtc != crtc_state->base.crtc)
                        continue;
 
-               if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
-                       return false;
+               if (crtc_state->ycbcr420) {
+                       const struct drm_hdmi_info *hdmi = &info->hdmi;
+
+                       if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
+                               return false;
+               } else {
+                       if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
+                               return false;
+               }
        }
 
        /* Display Wa #1139 */
@@ -1342,6 +1349,24 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
        return true;
 }
 
+static bool
+intel_hdmi_ycbcr420_config(struct drm_connector *connector,
+                          struct intel_crtc_state *config,
+                          int *clock_12bpc, int *clock_8bpc)
+{
+       if (!connector->ycbcr_420_allowed) {
+               DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+               return false;
+       }
+
+       /* YCBCR420 TMDS rate requirement is half the pixel clock */
+       config->port_clock /= 2;
+       *clock_12bpc /= 2;
+       *clock_8bpc /= 2;
+       config->ycbcr420 = true;
+       return true;
+}
+
 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
                               struct intel_crtc_state *pipe_config,
                               struct drm_connector_state *conn_state)
@@ -1349,7 +1374,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
-       struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc;
+       struct drm_connector *connector = conn_state->connector;
+       struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
        struct intel_digital_connector_state *intel_conn_state =
                to_intel_digital_connector_state(conn_state);
        int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
@@ -1379,6 +1405,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
                clock_12bpc *= 2;
        }
 
+       if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
+               if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
+                                               &clock_12bpc, &clock_8bpc)) {
+                       DRM_ERROR("Can't support YCBCR420 output\n");
+                       return false;
+               }
+       }
+
        if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
                pipe_config->has_pch_encoder = true;