drm/i915/icl: Program TA_TIMING_PARAM registers

This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).

v2: Changes
    - Don't use KHz() macro (Ville/Jani N)
    - Use newly defined bitfields

v3 by Jani:
 - Use intel_dsi_bitrate() in favor of a new field
 - Remove redundant parens

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c777092a748dfc973714399d8c19ed7a8c31a10.1539613303.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9602b6532028b6216b1a9b92568b357cdbc63fc8..f9df3a7fa66bc1b60d7371ef96a13b1f26e95264 100644 (file)
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -309,6 +309,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
                I915_WRITE(DSI_DATA_TIMING_PARAM(port),
                           intel_dsi->dphy_data_lane_reg);
        }
+
+       /*
+        * If DSI link operating at or below an 800 MHz,
+        * TA_SURE should be override and programmed to
+        * a value '0' inside TA_PARAM_REGISTERS otherwise
+        * leave all fields at HW default values.
+        */
+       if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+               for_each_dsi_port(port, intel_dsi->ports) {
+                       tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+                       tmp &= ~TA_SURE_MASK;
+                       tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+                       I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+                       /* shadow register inside display core */
+                       tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+                       tmp &= ~TA_SURE_MASK;
+                       tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+                       I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+               }
+       }
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)