sparc64: Add hardware capabilities for M8

This commit adds definitions for hardware
capabilities from both the Machine Descriptor and the
Compatibility Feature Register for M8 devices.

Orabug: 25555746

Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Reviewed-by: Shannon Nelson <shannon.nelson@oracle.com>
Reviewed-by: Khalid Aziz <khalid.aziz@oracle.com>
Signed-off-by: Allen Pais <allen.pais@oracle.com>

diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index b295b47ea2443aadb9e9bb87ed00fc04be0ce605..e5dd16074fc3221543b70982a944547c6fbbe0a6 100644 (file)
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -103,6 +103,8 @@
 
 /* Virtual Address Masking available */
 #define HWCAP_SPARC_VAMASK     0x0000000100000000UL
+/* SPARC6 insns available */
+#define HWCAP_SPARC_SPARC6     0x0000000200000000UL
 
 #define CORE_DUMP_USE_REGSET
 

diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 0c32514967218b4e6048c7e232e0048d4ef3979c..64a7002ee5447da6572f31f6f416b3425f0c895f 100644 (file)
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -397,13 +397,17 @@ static const char *hwcaps[] = {
        "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
        "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
        "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
-       "adp", "vis3b", "pause-nsec", "mwait", "sparc5", "vamask"
+       "adp", "vis3b", "pause-nsec", "mwait", "sparc5", "vamask", "sparc6"
 };
 
 static const char *crypto_hwcaps[] = {
+       /* These stings are as they appear in the
+        * Compatibility Feature Register.
+        */
        "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
        "sha512", "mpmul", "montmul", "montsqr", "crc32c", "xmpmul",
-       "xmontmul", "xmontsqr"
+       "xmontmul", "xmontsqr", "onaddsub", "onmul", "ondiv",
+       "dictunpack", "fpcmpshl", "rle", "sha3"
 };
 
 void cpucap_info(struct seq_file *m)
@@ -542,6 +546,7 @@ static void __init init_sparc64_elf_hwcap(void)
                    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                   sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
                        cap |= HWCAP_SPARC_BLKINIT;
                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
@@ -551,10 +556,12 @@ static void __init init_sparc64_elf_hwcap(void)
                    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                   sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
                    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
                        cap |= HWCAP_SPARC_N2;
                if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
-                   sun4v_chip_type == SUN4V_CHIP_SPARC_S7)
+                   sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                   sun4v_chip_type == SUN4V_CHIP_SPARC_M8)
                        cap |= (HWCAP_SPARC_VAMASK |
                                AV_SPARC_FSMULD);
        }
@@ -585,6 +592,7 @@ static void __init init_sparc64_elf_hwcap(void)
                            sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC64X)
                                cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
                                        AV_SPARC_ASI_BLK_INIT |
@@ -595,16 +603,19 @@ static void __init init_sparc64_elf_hwcap(void)
                            sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC64X)
                                cap |= (AV_SPARC_FMAF | AV_SPARC_HPC);
                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
                            sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
                            sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
                            sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
-                           sun4v_chip_type == SUN4V_CHIP_SPARC_S7)
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_M8)
                                cap |= AV_SPARC_VIS3;
                        if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
-                           sun4v_chip_type == SUN4V_CHIP_SPARC_S7)
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_S7 ||
+                           sun4v_chip_type == SUN4V_CHIP_SPARC_M8)
                                cap |= (AV_SPARC_IMA | AV_SPARC_PAUSE |
                                        AV_SPARC_CBCOND |
                                        HWCAP_SPARC_CRYPTO |
@@ -613,6 +624,8 @@ static void __init init_sparc64_elf_hwcap(void)
                                        HWCAP_SPARC_PAUSE_NSEC |
                                        HWCAP_SPARC_MWAIT |
                                        HWCAP_SPARC_SPARC5);
+                       if (sun4v_chip_type == SUN4V_CHIP_SPARC_M8)
+                               cap |= HWCAP_SPARC_SPARC6;
                }
        }
        sparc64_elf_hwcap = cap | mdesc_caps;