drm/xe/tlb: Convert register access to use xe_mmio

Stop using GT pointers for register access.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-83-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
index cca9cf536f769326e2993d9c66236a36f3fe9ba6..98616de0c5bb5ba2964e8893951e2ffefb466451 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
@@ -274,17 +274,19 @@ int xe_gt_tlb_invalidation_ggtt(struct xe_gt *gt)
 
                xe_gt_tlb_invalidation_fence_wait(&fence);
        } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
+               struct xe_mmio *mmio = &gt->mmio;
+
                if (IS_SRIOV_VF(xe))
                        return 0;
 
                xe_gt_WARN_ON(gt, xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));
                if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
-                       xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
+                       xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
                                        PVC_GUC_TLB_INV_DESC1_INVALIDATE);
-                       xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
+                       xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
                                        PVC_GUC_TLB_INV_DESC0_VALID);
                } else {
-                       xe_mmio_write32(gt, GUC_TLB_INV_CR,
+                       xe_mmio_write32(mmio, GUC_TLB_INV_CR,
                                        GUC_TLB_INV_CR_INVALIDATE);
                }
                xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);