if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
                cmd |= MI_READ_FLUSH;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
            (IS_G4X(dev) || IS_GEN5(dev)))
                cmd |= MI_INVALIDATE_ISP;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
        u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
        int ret;
 
-
-       ret = intel_ring_begin(ring, 6);
+       ret = intel_ring_begin(req, 6);
        if (ret)
                return ret;
 
        intel_ring_emit(ring, MI_NOOP);
        intel_ring_advance(ring);
 
-       ret = intel_ring_begin(ring, 6);
+       ret = intel_ring_begin(req, 6);
        if (ret)
                return ret;
 
                flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
        }
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
                gen7_render_ring_cs_stall_wa(req);
        }
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 6);
+       ret = intel_ring_begin(req, 6);
        if (ret)
                return ret;
 
        if (ret)
                return ret;
 
-       ret = intel_ring_begin(ring, (w->count * 2 + 2));
+       ret = intel_ring_begin(req, (w->count * 2 + 2));
        if (ret)
                return ret;
 
        num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 #undef MBOX_UPDATE_DWORDS
 
-       ret = intel_ring_begin(signaller, num_dwords);
+       ret = intel_ring_begin(signaller_req, num_dwords);
        if (ret)
                return ret;
 
        num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 #undef MBOX_UPDATE_DWORDS
 
-       ret = intel_ring_begin(signaller, num_dwords);
+       ret = intel_ring_begin(signaller_req, num_dwords);
        if (ret)
                return ret;
 
        num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
 #undef MBOX_UPDATE_DWORDS
 
-       ret = intel_ring_begin(signaller, num_dwords);
+       ret = intel_ring_begin(signaller_req, num_dwords);
        if (ret)
                return ret;
 
        if (ring->semaphore.signal)
                ret = ring->semaphore.signal(req, 4);
        else
-               ret = intel_ring_begin(ring, 4);
+               ret = intel_ring_begin(req, 4);
 
        if (ret)
                return ret;
        struct drm_i915_private *dev_priv = waiter->dev->dev_private;
        int ret;
 
-       ret = intel_ring_begin(waiter, 4);
+       ret = intel_ring_begin(waiter_req, 4);
        if (ret)
                return ret;
 
 
        WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 
-       ret = intel_ring_begin(waiter, 4);
+       ret = intel_ring_begin(waiter_req, 4);
        if (ret)
                return ret;
 
         * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
         * memory before requesting an interrupt.
         */
-       ret = intel_ring_begin(ring, 32);
+       ret = intel_ring_begin(req, 32);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
        u32 cs_offset = ring->scratch.gtt_offset;
        int ret;
 
-       ret = intel_ring_begin(ring, 6);
+       ret = intel_ring_begin(req, 6);
        if (ret)
                return ret;
 
                if (len > I830_BATCH_LIMIT)
                        return -ENOSPC;
 
-               ret = intel_ring_begin(ring, 6 + 2);
+               ret = intel_ring_begin(req, 6 + 2);
                if (ret)
                        return ret;
 
                offset = cs_offset;
        }
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
        return 0;
 }
 
-int intel_ring_begin(struct intel_engine_cs *ring,
+int intel_ring_begin(struct drm_i915_gem_request *req,
                     int num_dwords)
 {
-       struct drm_i915_gem_request *req;
-       struct drm_i915_private *dev_priv = ring->dev->dev_private;
+       struct intel_engine_cs *ring;
+       struct drm_i915_private *dev_priv;
        int ret;
 
+       WARN_ON(req == NULL);
+       ring = req->ring;
+       dev_priv = ring->dev->dev_private;
+
        ret = i915_gem_check_wedge(&dev_priv->gpu_error,
                                   dev_priv->mm.interruptible);
        if (ret)
        if (ret)
                return ret;
 
-       /* Preallocate the olr before touching the ring */
-       ret = i915_gem_request_alloc(ring, ring->default_context, &req);
-       if (ret)
-               return ret;
-
        ring->buffer->space -= num_dwords * sizeof(uint32_t);
        return 0;
 }
                return 0;
 
        num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
-       ret = intel_ring_begin(ring, num_dwords);
+       ret = intel_ring_begin(req, num_dwords);
        if (ret)
                return ret;
 
        uint32_t cmd;
        int ret;
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
                        !(dispatch_flags & I915_DISPATCH_SECURE);
        int ret;
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
        struct intel_engine_cs *ring = req->ring;
        int ret;
 
-       ret = intel_ring_begin(ring, 2);
+       ret = intel_ring_begin(req, 2);
        if (ret)
                return ret;
 
        uint32_t cmd;
        int ret;
 
-       ret = intel_ring_begin(ring, 4);
+       ret = intel_ring_begin(req, 4);
        if (ret)
                return ret;