[NISTC_INTB_ACK_REG]            = { 0x106, 2 },
        [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
        [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
-       [G_Command_Register(0)]         = { 0x10c, 2 },
-       [G_Command_Register(1)]         = { 0x10e, 2 },
+       [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
+       [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
        [AI_Command_1_Register]         = { 0x110, 2 },
        [AO_Command_1_Register]         = { 0x112, 2 },
        /*
 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
        [NITIO_G0_AUTO_INC]     = { G_Autoincrement_Register(0), 2 },
        [NITIO_G1_AUTO_INC]     = { G_Autoincrement_Register(1), 2 },
-       [NITIO_G0_CMD]          = { G_Command_Register(0), 2 },
-       [NITIO_G1_CMD]          = { G_Command_Register(1), 2 },
+       [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
+       [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
        [NITIO_G0_HW_SAVE]      = { G_HW_Save_Register(0), 4 },
        [NITIO_G1_HW_SAVE]      = { G_HW_Save_Register(1), 4 },
        [NITIO_G0_SW_SAVE]      = { G_Save_Register(0), 4 },
 
 #define NISTC_AO_CMD2_UPDATE2_PULSE    BIT(1)
 #define NISTC_AO_CMD2_START1_PULSE     BIT(0)
 
+#define NISTC_G0_CMD_REG               6
+#define NISTC_G1_CMD_REG               7
+
 #define AI_Status_1_Register           2
 #define Interrupt_A_St                         0x8000
 #define AI_FIFO_Full_St                                0x4000
 #define AI_External_Gate_Select(a)             ((a) & 0x1f)
 
 #define G_Autoincrement_Register(a)    (68+(a))
-#define G_Command_Register(a)          (6+(a))
 #define G_HW_Save_Register(a)          (8+(a)*2)
 #define G_HW_Save_Register_High(a)     (8+(a)*2)
 #define G_HW_Save_Register_Low(a)      (9+(a)*2)