clk: imx6ul: fix enet1 gate configuration

According to the "i.MX 6UltraLite Applications Processor Reference Manual,
Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
of PLL6. It is controlling ENET1 separately.

So, instead of this picture (implementation before this patch):
fec1 <- enet_ref (divider) <---------------------------,
                                                       |- pll6_enet (gate)
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´

we should have this one (after this patch):
fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
                                                       |- pll6_enet
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´

With this fix, the RMII reference clock will be turned off, after
setting network interface down on each separate interface
(ip l s dev eth0 down). Which was not working before, on system with both
FECs enabled.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 67a7a77ca54094b7e0f4b220ded53d1f022fecd7..c3c465c1b0e7720445278f7a4a1cc91dc60b87c4 100644 (file)
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        hws[IMX6UL_CLK_PLL3_USB_OTG]    = imx_clk_hw_gate("pll3_usb_otg",       "pll3_bypass", base + 0x10, 13);
        hws[IMX6UL_CLK_PLL4_AUDIO]      = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
        hws[IMX6UL_CLK_PLL5_VIDEO]      = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
-       hws[IMX6UL_CLK_PLL6_ENET]       = imx_clk_hw_gate("pll6_enet",  "pll6_bypass", base + 0xe0, 13);
+       hws[IMX6UL_CLK_PLL6_ENET]       = imx_clk_hw_fixed_factor("pll6_enet",  "pll6_bypass", 1, 1);
        hws[IMX6UL_CLK_PLL7_USB_HOST]   = imx_clk_hw_gate("pll7_usb_host",      "pll7_bypass", base + 0x20, 13);
 
        /*
@@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,        2);
        hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,        3);
 
-       hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+       hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0,
                        base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
        hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
                        base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
 
-       hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
+       hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13);
+       hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
        hws[IMX6UL_CLK_ENET_PTP_REF]    = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
        hws[IMX6UL_CLK_ENET_PTP]        = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
 

diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 79094338e6f1eb9846f00be6e382b16e805ea063..b44920f1edb0dbc89dc35163f97d8ea8f0a333b6 100644 (file)
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -256,7 +256,8 @@
 #define IMX6UL_CLK_GPIO4               247
 #define IMX6UL_CLK_GPIO5               248
 #define IMX6UL_CLK_MMDC_P1_IPG         249
+#define IMX6UL_CLK_ENET1_REF_125M      250
 
-#define IMX6UL_CLK_END                 250
+#define IMX6UL_CLK_END                 251
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */