#define AD7192_GPOCON_P1DAT    BIT(1) /* P1 state */
 #define AD7192_GPOCON_P0DAT    BIT(0) /* P0 state */
 
-#define AD7192_INT_FREQ_MHz    4915200
+#define AD7192_INT_FREQ_MHZ    4915200
 
 /* NOTE:
  * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
        switch (pdata->clock_source_sel) {
        case AD7192_CLK_EXT_MCLK1_2:
        case AD7192_CLK_EXT_MCLK2:
-               st->mclk = AD7192_INT_FREQ_MHz;
+               st->mclk = AD7192_INT_FREQ_MHZ;
                break;
        case AD7192_CLK_INT:
        case AD7192_CLK_INT_CO:
-               if (pdata->ext_clk_Hz)
-                       st->mclk = pdata->ext_clk_Hz;
+               if (pdata->ext_clk_hz)
+                       st->mclk = pdata->ext_clk_hz;
                else
-                       st->mclk = AD7192_INT_FREQ_MHz;
+                       st->mclk = AD7192_INT_FREQ_MHZ;
                        break;
        default:
                ret = -EINVAL;
 
 
 #define AD7280A_ALL_CELLS                              (0xAD << 16)
 
-#define AD7280A_MAX_SPI_CLK_Hz         700000 /* < 1MHz */
+#define AD7280A_MAX_SPI_CLK_HZ         700000 /* < 1MHz */
 #define AD7280A_MAX_CHAIN              8
 #define AD7280A_CELLS_PER_DEV          6
 #define AD7280A_BITS                   12
 
        ad7280_crc8_build_table(st->crc_tab);
 
-       st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_Hz;
+       st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_HZ;
        st->spi->mode = SPI_MODE_1;
        spi_setup(st->spi);