]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
bnxt_en: Fix IRQ coalescing regression.
authorMichael Chan <michael.chan@broadcom.com>
Fri, 3 Nov 2017 07:32:39 +0000 (03:32 -0400)
committerJack Vogel <jack.vogel@oracle.com>
Fri, 9 Mar 2018 05:01:30 +0000 (21:01 -0800)
Orabug: 2764835527648339

Recent IRQ coalescing clean up has removed a guard-rail for the max DMA
buffer coalescing value.  This is a 6-bit value and must not be 0.  We
already have a check for 0 but 64 is equivalent to 0 and will cause
non-stop interrupts.  Fix it by adding the proper check.

Fixes: f8503969d27b ("bnxt_en: Refactor and simplify coalescing code.")
Reported-by: Andy Gospodarek <gospo@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit b153cbc507946f52d5aa687fd64f45d82cb36a3b)
Signed-off-by: Brian Maly <brian.maly@oracle.com>
Reviewed-by: Jack Vogel <jack.vogel@oracle.com>
drivers/net/ethernet/broadcom/bnxt/bnxt.c

index b1e4b316877e6fa8f93d264f91e33efb3fcbf9a4..2a5d480837999af00ca26b3dbeaaa6d8ff97ce84 100644 (file)
@@ -4522,9 +4522,13 @@ static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
 
        val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
        req->num_cmpl_aggr_int = cpu_to_le16(val);
+
+       /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
+       val = min_t(u16, val, 63);
        req->num_cmpl_dma_aggr = cpu_to_le16(val);
 
-       val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, max);
+       /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
+       val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
        req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
 
        tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);