The PLL parameters in rate table should be directly compared with
those read from PLL registers instead of the cooked ones.
Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220609132902.3504651-6-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
 
        mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
 
        rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
-       rdiv = rdiv + 1;
        odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
-       switch (odiv) {
-       case 0:
-               odiv = 2;
-               break;
-       case 1:
-               odiv = 3;
-               break;
-       default:
-               break;
-       }
 
        /*
         * Sometimes, the recalculated rate has deviation due to
        if (rate)
                return (unsigned long)rate;
 
+       rdiv = rdiv + 1;
+
+       switch (odiv) {
+       case 0:
+               odiv = 2;
+               break;
+       case 1:
+               odiv = 3;
+               break;
+       default:
+               break;
+       }
+
        /* Fvco = Fref * (MFI + MFN / MFD) */
        fvco = fvco * mfi * mfd + fvco * mfn;
        do_div(fvco, mfd * rdiv * odiv);