]> www.infradead.org Git - users/hch/misc.git/commitdiff
drm/amdgpu/mes: clean up SDMA HQD loop
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 19 Mar 2025 14:03:31 +0000 (10:03 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Mar 2025 16:16:35 +0000 (12:16 -0400)
Follow the same logic as the other IP types.

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

index 230d0d05c65e8b717ab92cd4130c72f0d4b9f6c2..85f774063f9b1078af1c51532e7d944cdcde6174 100644 (file)
@@ -154,11 +154,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
                adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
 
        for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
-               /* zero sdma_hqd_mask for non-existent engine */
-               if (adev->sdma.num_instances == 1)
-                       adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
-               else
-                       adev->mes.sdma_hqd_mask[i] = 0xfc;
+               if (i >= adev->sdma.num_instances)
+                       break;
+               adev->mes.sdma_hqd_mask[i] = 0xfc;
        }
 
        for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {