amdgpu_ras_check_supported(adev, &con->hw_supported,
                        &con->supported);
        if (!con->hw_supported) {
-               amdgpu_ras_set_context(adev, NULL);
-               kfree(con);
-               return 0;
+               r = 0;
+               goto err_out;
        }
 
        con->features = 0;
        if (adev->nbio.funcs->init_ras_controller_interrupt) {
                r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
                if (r)
-                       return r;
+                       goto err_out;
        }
 
        if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
                r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
                if (r)
-                       return r;
+                       goto err_out;
        }
 
        amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
 
-       if (amdgpu_ras_fs_init(adev))
-               goto fs_out;
+       if (amdgpu_ras_fs_init(adev)) {
+               r = -EINVAL;
+               goto err_out;
+       }
 
        dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
                        "hardware ability[%x] ras_mask[%x]\n",
                        con->hw_supported, con->supported);
        return 0;
-fs_out:
+err_out:
        amdgpu_ras_set_context(adev, NULL);
        kfree(con);
 
-       return -EINVAL;
+       return r;
 }
 
 /* helper function to handle common stuff in ip late init phase */