static void cik_program_aspm(struct radeon_device *rdev);
 static void cik_init_pg(struct radeon_device *rdev);
 static void cik_init_cg(struct radeon_device *rdev);
+static void cik_uvd_resume(struct radeon_device *rdev);
 
 /* get temperature in millidegrees */
 int ci_get_temp(struct radeon_device *rdev)
                return r;
        }
 
-       r = cik_uvd_resume(rdev);
+       r = radeon_uvd_resume(rdev);
        if (!r) {
+               cik_uvd_resume(rdev);
                r = radeon_fence_driver_start_ring(rdev,
                                                   R600_RING_TYPE_UVD_INDEX);
                if (r)
                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                     0, 0xfffff, RADEON_CP_PACKET2);
                if (!r)
-                       r = r600_uvd_init(rdev);
+                       r = r600_uvd_init(rdev, true);
                if (r)
                        DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
        }
        return r;
 }
 
-int cik_uvd_resume(struct radeon_device *rdev)
+static void cik_uvd_resume(struct radeon_device *rdev)
 {
        uint64_t addr;
        uint32_t size;
-       int r;
-
-       r = radeon_uvd_resume(rdev);
-       if (r)
-               return r;
 
        /* programm the VCPU memory controller bits 0-27 */
        addr = rdev->uvd.gpu_addr >> 3;
        addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
        WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 
-       return 0;
 }
 
 static void cik_pcie_gen3_enable(struct radeon_device *rdev)
 
 /*
  * UVD
  */
-int r600_uvd_rbc_start(struct radeon_device *rdev)
+static int r600_uvd_rbc_start(struct radeon_device *rdev, bool ring_test)
 {
        struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
        uint64_t rptr_addr;
        rb_bufsz = (0x1 << 8) | rb_bufsz;
        WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
 
-       ring->ready = true;
-       r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
-       if (r) {
-               ring->ready = false;
-               return r;
-       }
+       if (ring_test) {
+               ring->ready = true;
+               r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
+               if (r) {
+                       ring->ready = false;
+                       return r;
+               }
 
-       r = radeon_ring_lock(rdev, ring, 10);
-       if (r) {
-               DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
-               return r;
-       }
+               r = radeon_ring_lock(rdev, ring, 10);
+               if (r) {
+                       DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
+                       return r;
+               }
 
-       tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
-       radeon_ring_write(ring, tmp);
-       radeon_ring_write(ring, 0xFFFFF);
+               tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
+               radeon_ring_write(ring, tmp);
+               radeon_ring_write(ring, 0xFFFFF);
 
-       tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
-       radeon_ring_write(ring, tmp);
-       radeon_ring_write(ring, 0xFFFFF);
+               tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
+               radeon_ring_write(ring, tmp);
+               radeon_ring_write(ring, 0xFFFFF);
 
-       tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
-       radeon_ring_write(ring, tmp);
-       radeon_ring_write(ring, 0xFFFFF);
+               tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
+               radeon_ring_write(ring, tmp);
+               radeon_ring_write(ring, 0xFFFFF);
 
-       /* Clear timeout status bits */
-       radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
-       radeon_ring_write(ring, 0x8);
+               /* Clear timeout status bits */
+               radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
+               radeon_ring_write(ring, 0x8);
 
-       radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
-       radeon_ring_write(ring, 3);
+               radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
+               radeon_ring_write(ring, 3);
 
-       radeon_ring_unlock_commit(rdev, ring);
+               radeon_ring_unlock_commit(rdev, ring);
+       }
 
        return 0;
 }
 
-void r600_uvd_stop(struct radeon_device *rdev)
+void r600_do_uvd_stop(struct radeon_device *rdev)
 {
-       struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
-
        /* force RBC into idle state */
        WREG32(UVD_RBC_RB_CNTL, 0x11010101);
 
        /* Unstall UMC and register bus */
        WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
        WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
+}
 
+void r600_uvd_stop(struct radeon_device *rdev)
+{
+       struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
+
+       r600_do_uvd_stop(rdev);
        ring->ready = false;
 }
 
-int r600_uvd_init(struct radeon_device *rdev)
+int r600_uvd_init(struct radeon_device *rdev, bool ring_test)
 {
        int i, j, r;
        /* disable byte swapping */
 
        if (r) {
                DRM_ERROR("UVD not responding, giving up!!!\n");
-               radeon_set_uvd_clocks(rdev, 0, 0);
-               return r;
+               goto done;
        }
 
        /* enable interupt */
        WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
 
-       r = r600_uvd_rbc_start(rdev);
+       r = r600_uvd_rbc_start(rdev, ring_test);
        if (!r)
                DRM_INFO("UVD initialized successfully.\n");
 
+done:
        /* lower clocks again */
        radeon_set_uvd_clocks(rdev, 0, 0);
 
 
                                                       struct seq_file *m);
 
 /* uvd */
-int r600_uvd_init(struct radeon_device *rdev);
-int r600_uvd_rbc_start(struct radeon_device *rdev);
+int r600_uvd_init(struct radeon_device *rdev, bool ring_test);
 void r600_uvd_stop(struct radeon_device *rdev);
 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 void r600_uvd_fence_emit(struct radeon_device *rdev,
 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-int cik_uvd_resume(struct radeon_device *rdev);
 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
                              struct radeon_fence *fence);
 void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,