{ 0x8306, 0x0a },
        };
 
-       if (mode->hdisplay == 3840)
+       if (lt9611->dsi1_node)
                reg_cfg[1].def = 0x03;
 
        return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
                { 0x832d, 0x38 },
                { 0x8331, 0x08 },
        };
-       const struct reg_sequence reg_cfg2[] = {
-               { 0x830b, 0x03 },
-               { 0x830c, 0xd0 },
-               { 0x8348, 0x03 },
-               { 0x8349, 0xe0 },
-               { 0x8324, 0x72 },
-               { 0x8325, 0x00 },
-               { 0x832a, 0x01 },
-               { 0x834a, 0x10 },
-       };
        u8 pol = 0x10;
 
        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
                pol |= 0x1;
        regmap_write(lt9611->regmap, 0x831d, pol);
 
-       if (mode->hdisplay == 3840)
-               regmap_multi_reg_write(lt9611->regmap, reg_cfg2, ARRAY_SIZE(reg_cfg2));
-       else
-               regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
+       regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
+       if (lt9611->dsi1_node) {
+               unsigned int hact = mode->hdisplay;
+
+               hact >>= 2;
+               hact += 0x50;
+               hact = min(hact, 0x3e0U);
+               regmap_write(lt9611->regmap, 0x830b, hact / 256);
+               regmap_write(lt9611->regmap, 0x830c, hact % 256);
+               regmap_write(lt9611->regmap, 0x8348, hact / 256);
+               regmap_write(lt9611->regmap, 0x8349, hact % 256);
+       }
 
        regmap_write(lt9611->regmap, 0x8326, pcr_m);