Supported ports in ethtool <eth1> are displayed based on media type.
For media type fibre and twinaxial, port type is "FIBRE". Media type
Base-T is "TP" and media KR is "Backplane".
V1->V2:
Corrected the subject.
Signed-off-by: Rahul Verma <rahulv@marvell.com>
Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 
        switch (media_type) {
        case MEDIA_DA_TWINAX:
+               *if_capability |= QED_LM_FIBRE_BIT;
                if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
                        *if_capability |= QED_LM_20000baseKR2_Full_BIT;
                /* For DAC media multiple speed capabilities are supported*/
                        *if_capability |= QED_LM_100000baseCR4_Full_BIT;
                break;
        case MEDIA_BASE_T:
+               *if_capability |= QED_LM_TP_BIT;
                if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
                        if (capability &
                            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
                        }
                }
                if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
+                       *if_capability |= QED_LM_FIBRE_BIT;
                        if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET)
                                *if_capability |= QED_LM_1000baseT_Full_BIT;
                        if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET)
        case MEDIA_SFPP_10G_FIBER:
        case MEDIA_XFP_FIBER:
        case MEDIA_MODULE_FIBER:
+               *if_capability |= QED_LM_FIBRE_BIT;
                if (capability &
                    NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
                        if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) ||
 
                break;
        case MEDIA_KR:
+               *if_capability |= QED_LM_Backplane_BIT;
                if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
                        *if_capability |= QED_LM_20000baseKR2_Full_BIT;
                if (capability &
                if_link->link_up = true;
 
        /* TODO - at the moment assume supported and advertised speed equal */
-       if_link->supported_caps = QED_LM_FIBRE_BIT;
        if (link_caps.default_speed_autoneg)
                if_link->supported_caps |= QED_LM_Autoneg_BIT;
        if (params.pause.autoneg ||
 
 };
 
 static const struct qede_link_mode_mapping qed_lm_map[] = {
+       {QED_LM_FIBRE_BIT, ETHTOOL_LINK_MODE_FIBRE_BIT},
        {QED_LM_Autoneg_BIT, ETHTOOL_LINK_MODE_Autoneg_BIT},
        {QED_LM_Asym_Pause_BIT, ETHTOOL_LINK_MODE_Asym_Pause_BIT},
        {QED_LM_Pause_BIT, ETHTOOL_LINK_MODE_Pause_BIT},
        {QED_LM_1000baseT_Full_BIT, ETHTOOL_LINK_MODE_1000baseT_Full_BIT},
        {QED_LM_10000baseT_Full_BIT, ETHTOOL_LINK_MODE_10000baseT_Full_BIT},
-       {QED_LM_2500baseX_Full_BIT, ETHTOOL_LINK_MODE_2500baseX_Full_BIT},
+       {QED_LM_TP_BIT, ETHTOOL_LINK_MODE_TP_BIT},
        {QED_LM_Backplane_BIT, ETHTOOL_LINK_MODE_Backplane_BIT},
        {QED_LM_1000baseKX_Full_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
        {QED_LM_10000baseKX4_Full_BIT, ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT},
 
        QED_LM_40000baseLR4_Full_BIT = BIT(9),
        QED_LM_50000baseKR2_Full_BIT = BIT(10),
        QED_LM_100000baseKR4_Full_BIT = BIT(11),
-       QED_LM_2500baseX_Full_BIT = BIT(12),
+       QED_LM_TP_BIT = BIT(12),
        QED_LM_Backplane_BIT = BIT(13),
        QED_LM_1000baseKX_Full_BIT = BIT(14),
        QED_LM_10000baseKX4_Full_BIT = BIT(15),