clocksource/drivers/mips-gic-timer: Correct sched_clock width

Counter width of GIC is configurable and can be read from a
register.

Use width value from the register for sched_clock.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Link: https://lore.kernel.org/r/20240612-mips-clks-v2-7-a57e6f49f3db@flygoat.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 7a03d94c028a9b5a2fa9d0893e037afa7fcc9e3d..110347707ff980162e15c8f6ecced5d765d28cf9 100644 (file)
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -19,6 +19,7 @@
 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
 static int gic_timer_irq;
 static unsigned int gic_frequency;
+static unsigned int gic_count_width;
 static bool __read_mostly gic_clock_unstable;
 
 static void gic_clocksource_unstable(char *reason);
@@ -186,15 +187,14 @@ static void gic_clocksource_unstable(char *reason)
 
 static int __init __gic_clocksource_init(void)
 {
-       unsigned int count_width;
        int ret;
 
        /* Set clocksource mask. */
-       count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
-       count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
-       count_width *= 4;
-       count_width += 32;
-       gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
+       gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
+       gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
+       gic_count_width *= 4;
+       gic_count_width += 32;
+       gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width);
 
        /* Calculate a somewhat reasonable rating value. */
        if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
@@ -264,7 +264,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
        if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
                sched_clock_register(mips_cm_is64 ?
                                     gic_read_count_64 : gic_read_count_2x32,
-                                    64, gic_frequency);
+                                    gic_count_width, gic_frequency);
        }
 
        return 0;