tg3: Scale back code that modifies MRRS

Tg3 normally gets a performance boost by increasing the PCI Maximum Read
Request Size (MRRS) to 4k.  Unfortunately, this is causing some problems
on particular hardware platforms.  This patch removes all code that
modifies the MRRS except for one case.

As part of a solution to fix an internal FIFO problem on the 5719, the
driver artificially capped the MRRS to 2k for the entire 5719, and later
5720, ASIC revs.  This was overly aggressive and only really needed to
be done for the 5719 A0.  In the spirit of the rest of this patch, the
driver will only reprogram the MRRS for this device if the value exceeds
the 2k cap.

(cherry picked from commit 2c55a3d08ade44a778c182c220a7907ec65d5fb8)
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Joe Jin <joe.jin@oracle.com>

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d8132f76930b403a90e555d126d7ee3ea71d8813..f497d415db1f8d8087a003f7a481f9b57c3b3696 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7643,15 +7643,11 @@ static void tg3_restore_pci_state(struct tg3 *tp)
 
        pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
-               if (tg3_flag(tp, PCI_EXPRESS))
-                       pcie_set_readrq(tp->pdev, tp->pcie_readrq);
-               else {
-                       pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
-                                             tp->pci_cacheline_sz);
-                       pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
-                                             tp->pci_lat_timer);
-               }
+       if (!tg3_flag(tp, PCI_EXPRESS)) {
+               pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
+                                     tp->pci_cacheline_sz);
+               pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
+                                     tp->pci_lat_timer);
        }
 
        /* Make sure PCI-X relaxed ordering bit is clear. */
@@ -7836,8 +7832,6 @@ static int tg3_chip_reset(struct tg3 *tp)
                                      pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
                                      val16);
 
-               pcie_set_readrq(tp->pdev, tp->pcie_readrq);
-
                /* Clear error status */
                pci_write_config_word(tp->pdev,
                                      pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
@@ -14081,12 +14075,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
                tg3_flag_set(tp, PCI_EXPRESS);
 
-               tp->pcie_readrq = 4096;
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
-                       tp->pcie_readrq = 2048;
-
-               pcie_set_readrq(tp->pdev, tp->pcie_readrq);
+               if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
+                       int readrq = pcie_get_readrq(tp->pdev);
+                       if (readrq > 2048)
+                               pcie_set_readrq(tp->pdev, 2048);
+               }
 
                pci_read_config_word(tp->pdev,
                                     pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,