irqchip/armada-370-xp: Drop _OFFS suffix from some register constants

Some register constants have the _OFFS suffix and some do not. Drop it
to be more consistent.

Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/all/20240708151801.11592-2-kabel@kernel.org

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index dce2b80bf439cc5c1c89cad2101e52b9f73cbff5..66d6a2ebc8a53853cef34e8f37cc5f9999ed3a3d 100644 (file)
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -66,15 +66,14 @@
  *                   device
  *
  * The "global interrupt mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
- * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
- * to "main_int_base".
+ * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
+ * registers, which are relative to "main_int_base".
  *
  * The "per-CPU mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_MASK_OFFS and
- * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
- * "per_cpu_int_base". This base address points to a special address,
- * which automatically accesses the registers of the current CPU.
+ * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
+ * registers, which are relative to "per_cpu_int_base". This base
+ * address points to a special address, which automatically accesses
+ * the registers of the current CPU.
  *
  * The per-CPU mask/unmask can also be adjusted using the global
  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
@@ -118,21 +117,21 @@
 
 /* Registers relative to main_int_base */
 #define ARMADA_370_XP_INT_CONTROL              (0x00)
-#define ARMADA_370_XP_SW_TRIG_INT_OFFS         (0x04)
-#define ARMADA_370_XP_INT_SET_ENABLE_OFFS      (0x30)
-#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS    (0x34)
+#define ARMADA_370_XP_SW_TRIG_INT              (0x04)
+#define ARMADA_370_XP_INT_SET_ENABLE           (0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE         (0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)      (0x100 + irq*4)
 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK      0xF
 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)  ((BIT(0) | BIT(8)) << cpuid)
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS      (0x08)
-#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS                (0x0c)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE           (0x08)
+#define ARMADA_370_XP_IN_DRBEL_MSK             (0x0c)
 #define ARMADA_375_PPI_CAUSE                   (0x10)
-#define ARMADA_370_XP_CPU_INTACK_OFFS          (0x44)
-#define ARMADA_370_XP_INT_SET_MASK_OFFS                (0x48)
-#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS      (0x4C)
-#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS     (0x54)
+#define ARMADA_370_XP_CPU_INTACK               (0x44)
+#define ARMADA_370_XP_INT_SET_MASK             (0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK           (0x4C)
+#define ARMADA_370_XP_INT_FABRIC_MASK          (0x54)
 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)      (1 << cpu)
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS         (28)
@@ -220,11 +219,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
        irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        if (!is_percpu_irq(hwirq))
-               writel(hwirq, main_int_base +
-                               ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+               writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
        else
-               writel(hwirq, per_cpu_int_base +
-                               ARMADA_370_XP_INT_SET_MASK_OFFS);
+               writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
 }
 
 static void armada_370_xp_irq_unmask(struct irq_data *d)
@@ -232,11 +229,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
        irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        if (!is_percpu_irq(hwirq))
-               writel(hwirq, main_int_base +
-                               ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+               writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
        else
-               writel(hwirq, per_cpu_int_base +
-                               ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+               writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 #ifdef CONFIG_PCI_MSI
@@ -329,19 +324,18 @@ static void armada_370_xp_msi_reenable_percpu(void)
        u32 reg;
 
        /* Enable MSI doorbell mask and combined cpu local interrupt */
-       reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
        reg |= msi_doorbell_mask();
-       writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
        /* Unmask local doorbell interrupt */
-       writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+       writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 static int armada_370_xp_msi_init(struct device_node *node,
                                  phys_addr_t main_int_phys_base)
 {
-       msi_doorbell_addr = main_int_phys_base +
-               ARMADA_370_XP_SW_TRIG_INT_OFFS;
+       msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
 
        armada_370_xp_msi_inner_domain =
                irq_domain_add_linear(NULL, msi_doorbell_size(),
@@ -362,7 +356,7 @@ static int armada_370_xp_msi_init(struct device_node *node,
 
        /* Unmask low 16 MSI irqs on non-IPI platforms */
        if (!is_ipi_available())
-               writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+               writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 
        return 0;
 }
@@ -391,7 +385,7 @@ static void armada_xp_mpic_perf_init(void)
 
        /* Enable Performance Counter Overflow interrupts */
        writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
-              per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
+              per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
 }
 
 #ifdef CONFIG_SMP
@@ -400,17 +394,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
        u32 reg;
-       reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
        reg &= ~BIT(d->hwirq);
-       writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
        u32 reg;
-       reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
        reg |= BIT(d->hwirq);
-       writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,
@@ -431,12 +425,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 
        /* submit softirq */
        writel((map << 8) | d->hwirq, main_int_base +
-               ARMADA_370_XP_SW_TRIG_INT_OFFS);
+               ARMADA_370_XP_SW_TRIG_INT);
 }
 
 static void armada_370_xp_ipi_ack(struct irq_data *d)
 {
-       writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+       writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 }
 
 static struct irq_chip ipi_irqchip = {
@@ -539,19 +533,19 @@ static void armada_xp_mpic_smp_cpu_init(void)
        nr_irqs = (control >> 2) & 0x3ff;
 
        for (i = 0; i < nr_irqs; i++)
-               writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+               writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
 
        if (!is_ipi_available())
                return;
 
        /* Disable all IPIs */
-       writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
        /* Clear pending IPIs */
-       writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+       writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 
        /* Unmask IPI interrupt */
-       writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+       writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 static void armada_xp_mpic_reenable_percpu(void)
@@ -622,9 +616,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
        armada_370_xp_irq_mask(irq_get_irq_data(virq));
        if (!is_percpu_irq(hw))
                writel(hw, per_cpu_int_base +
-                       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+                       ARMADA_370_XP_INT_CLEAR_MASK);
        else
-               writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+               writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
        irq_set_status_flags(virq, IRQ_LEVEL);
 
        if (is_percpu_irq(hw)) {
@@ -651,12 +645,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
        u32 msimask, msinr;
 
-       msimask = readl_relaxed(per_cpu_int_base +
-                               ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+       msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
        msimask &= msi_doorbell_mask();
 
-       writel(~msimask, per_cpu_int_base +
-              ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+       writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 
        for (msinr = msi_doorbell_start();
             msinr < msi_doorbell_end(); msinr++) {
@@ -712,7 +704,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
        do {
                irqstat = readl_relaxed(per_cpu_int_base +
-                                       ARMADA_370_XP_CPU_INTACK_OFFS);
+                                       ARMADA_370_XP_CPU_INTACK);
                irqnr = irqstat & 0x3FF;
 
                if (irqnr > 1022)
@@ -735,7 +727,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
                        int ipi;
 
                        ipimask = readl_relaxed(per_cpu_int_base +
-                                               ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
+                                               ARMADA_370_XP_IN_DRBEL_CAUSE)
                                & IPI_DOORBELL_MASK;
 
                        for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
@@ -748,8 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-       doorbell_mask_reg = readl(per_cpu_int_base +
-                                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+       doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
        return 0;
 }
 
@@ -774,13 +765,13 @@ static void armada_370_xp_mpic_resume(void)
                if (!is_percpu_irq(irq)) {
                        /* Non per-CPU interrupts */
                        writel(irq, per_cpu_int_base +
-                              ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+                              ARMADA_370_XP_INT_CLEAR_MASK);
                        if (!irqd_irq_disabled(data))
                                armada_370_xp_irq_unmask(data);
                } else {
                        /* Per-CPU interrupts */
                        writel(irq, main_int_base +
-                              ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+                              ARMADA_370_XP_INT_SET_ENABLE);
 
                        /*
                         * Re-enable on the current CPU,
@@ -794,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
 
        /* Reconfigure doorbells for IPIs and MSIs */
        writel(doorbell_mask_reg,
-              per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+              per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
        if (is_ipi_available()) {
                src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
@@ -805,9 +796,9 @@ static void armada_370_xp_mpic_resume(void)
        }
 
        if (src0)
-               writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+               writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
        if (src1)
-               writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+               writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 
        if (is_ipi_available())
                ipi_resume();
@@ -847,7 +838,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
        nr_irqs = (control >> 2) & 0x3ff;
 
        for (i = 0; i < nr_irqs; i++)
-               writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+               writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
 
        armada_370_xp_mpic_domain =
                irq_domain_add_linear(node, nr_irqs,