#ifndef _I40E_ADMINQ_H_
 #define _I40E_ADMINQ_H_
 
+#include <linux/mutex.h>
 #include "i40e_alloc.h"
-#include "i40e_osdep.h"
 #include "i40e_adminq_cmd.h"
 
 #define I40E_ADMINQ_DESC(R, i)   \
 
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2023 Intel Corporation. */
+
+#ifndef _I40E_DEBUG_H_
+#define _I40E_DEBUG_H_
+
+#include <linux/dev_printk.h>
+
+/* debug masks - set these bits in hw->debug_mask to control output */
+enum i40e_debug_mask {
+       I40E_DEBUG_INIT                 = 0x00000001,
+       I40E_DEBUG_RELEASE              = 0x00000002,
+
+       I40E_DEBUG_LINK                 = 0x00000010,
+       I40E_DEBUG_PHY                  = 0x00000020,
+       I40E_DEBUG_HMC                  = 0x00000040,
+       I40E_DEBUG_NVM                  = 0x00000080,
+       I40E_DEBUG_LAN                  = 0x00000100,
+       I40E_DEBUG_FLOW                 = 0x00000200,
+       I40E_DEBUG_DCB                  = 0x00000400,
+       I40E_DEBUG_DIAG                 = 0x00000800,
+       I40E_DEBUG_FD                   = 0x00001000,
+       I40E_DEBUG_PACKAGE              = 0x00002000,
+       I40E_DEBUG_IWARP                = 0x00F00000,
+       I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
+       I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
+       I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
+       I40E_DEBUG_AQ_COMMAND           = 0x06000000,
+       I40E_DEBUG_AQ                   = 0x0F000000,
+
+       I40E_DEBUG_USER                 = 0xF0000000,
+
+       I40E_DEBUG_ALL                  = 0xFFFFFFFF
+};
+
+struct i40e_hw;
+struct device *i40e_hw_to_dev(struct i40e_hw *hw);
+
+#define hw_dbg(hw, S, A...) dev_dbg(i40e_hw_to_dev(hw), S, ##A)
+
+#define i40e_debug(h, m, s, ...)                               \
+do {                                                           \
+       if (((m) & (h)->debug_mask))                            \
+               dev_info(i40e_hw_to_dev(hw), s, ##__VA_ARGS__); \
+} while (0)
+
+#endif /* _I40E_DEBUG_H_ */
 
 /* Copyright(c) 2013 - 2018 Intel Corporation. */
 
 #include "i40e.h"
-#include "i40e_osdep.h"
 #include "i40e_register.h"
 #include "i40e_alloc.h"
 #include "i40e_hmc.h"
 
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2023 Intel Corporation. */
+
+#ifndef _I40E_IO_H_
+#define _I40E_IO_H_
+
+/* get readq/writeq support for 32 bit kernels, use the low-first version */
+#include <linux/io-64-nonatomic-lo-hi.h>
+
+#define wr32(a, reg, value)    writel((value), ((a)->hw_addr + (reg)))
+#define rd32(a, reg)           readl((a)->hw_addr + (reg))
+
+#define rd64(a, reg)           readq((a)->hw_addr + (reg))
+#define i40e_flush(a)          readl((a)->hw_addr + I40E_GLGEN_STAT)
+
+#endif /* _I40E_IO_H_ */
 
 /* Copyright(c) 2013 - 2018 Intel Corporation. */
 
 #include "i40e.h"
-#include "i40e_osdep.h"
 #include "i40e_register.h"
 #include "i40e_type.h"
 #include "i40e_hmc.h"
 
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright(c) 2013 - 2018 Intel Corporation. */
-
-#ifndef _I40E_OSDEP_H_
-#define _I40E_OSDEP_H_
-
-#include <linux/types.h>
-#include <linux/if_ether.h>
-#include <linux/if_vlan.h>
-#include <linux/tcp.h>
-#include <linux/pci.h>
-#include <linux/highuid.h>
-
-/* get readq/writeq support for 32 bit kernels, use the low-first version */
-#include <linux/io-64-nonatomic-lo-hi.h>
-
-/* File to be the magic between shared code and
- * actual OS primitives
- */
-
-struct i40e_hw;
-struct device *i40e_hw_to_dev(struct i40e_hw *hw);
-
-#define hw_dbg(hw, S, A...) dev_dbg(i40e_hw_to_dev(hw), S, ##A)
-
-#define wr32(a, reg, value)    writel((value), ((a)->hw_addr + (reg)))
-#define rd32(a, reg)           readl((a)->hw_addr + (reg))
-
-#define rd64(a, reg)           readq((a)->hw_addr + (reg))
-#define i40e_flush(a)          readl((a)->hw_addr + I40E_GLGEN_STAT)
-
-#define i40e_debug(h, m, s, ...)                               \
-do {                                                           \
-       if (((m) & (h)->debug_mask))                            \
-               pr_info("i40e %02x:%02x.%x " s,                 \
-                       (h)->bus.bus_id, (h)->bus.device,       \
-                       (h)->bus.func, ##__VA_ARGS__);          \
-} while (0)
-
-#endif /* _I40E_OSDEP_H_ */
 
 
 #include "i40e_type.h"
 #include "i40e_alloc.h"
+#include "i40e_debug.h"
 #include <linux/avf/virtchnl.h>
 
 /* Prototypes for shared code functions that are not in
 
 #ifndef _I40E_TYPE_H_
 #define _I40E_TYPE_H_
 
-#include "i40e_osdep.h"
+#include <linux/delay.h>
+#include <linux/if_ether.h>
+#include "i40e_io.h"
 #include "i40e_register.h"
 #include "i40e_adminq.h"
 #include "i40e_hmc.h"
 #define I40E_QTX_CTL_VM_QUEUE  0x1
 #define I40E_QTX_CTL_PF_QUEUE  0x2
 
-/* debug masks - set these bits in hw->debug_mask to control output */
-enum i40e_debug_mask {
-       I40E_DEBUG_INIT                 = 0x00000001,
-       I40E_DEBUG_RELEASE              = 0x00000002,
-
-       I40E_DEBUG_LINK                 = 0x00000010,
-       I40E_DEBUG_PHY                  = 0x00000020,
-       I40E_DEBUG_HMC                  = 0x00000040,
-       I40E_DEBUG_NVM                  = 0x00000080,
-       I40E_DEBUG_LAN                  = 0x00000100,
-       I40E_DEBUG_FLOW                 = 0x00000200,
-       I40E_DEBUG_DCB                  = 0x00000400,
-       I40E_DEBUG_DIAG                 = 0x00000800,
-       I40E_DEBUG_FD                   = 0x00001000,
-       I40E_DEBUG_PACKAGE              = 0x00002000,
-       I40E_DEBUG_IWARP                = 0x00F00000,
-       I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
-       I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
-       I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
-       I40E_DEBUG_AQ_COMMAND           = 0x06000000,
-       I40E_DEBUG_AQ                   = 0x0F000000,
-
-       I40E_DEBUG_USER                 = 0xF0000000,
-
-       I40E_DEBUG_ALL                  = 0xFFFFFFFF
-};
-
 #define I40E_MDIO_CLAUSE22_STCODE_MASK         I40E_GLGEN_MSCA_STCODE_MASK
 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK   I40E_GLGEN_MSCA_OPCODE_MASK(1)
 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK    I40E_GLGEN_MSCA_OPCODE_MASK(2)