#define __CONFIG_H
/* Enable debug prints */
-#undef DEBUG /* General debug */
-#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
+#undef DEBUG /* General debug */
+#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/*****************************************************************************
*
*****************************************************************************/
/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
+#define CONFIG_8260_CLKIN (33 * 1000 * 1000)
/*-----------------------------------------------------------------------
* MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
* 0x6 0x1 66 133 266 Close Close Open
* 0x6 0x2 66 133 300 Close Open Close
*/
-#define CFG_SBC_MODCK_H 0x05
+#define CFG_SBC_MODCK_H 0x02
/* Define this if you want to boot from 0x00000100. If you don't define
* this, you will need to program the bootloader to 0xfff00000, and
#define CFG_LED_BASE 0xa0000000
-/*
+/*
* SBC8260 with 16 MB DIMM:
- *
+ *
* 0x0000 0000 Exception Vector code, 8k
- * :
+ * :
* 0x0000 1FFF
* 0x0000 2000 Free for Application Use
- * :
- * :
+ * :
+ * :
*
- * :
- * :
+ * :
+ * :
* 0x00F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
+ * Monitor Stack Buffer (0x80)
* 0x00F5 FFB0 Board Info Data
* 0x00F6 0000 Malloc Arena
- * : CFG_ENV_SECT_SIZE, 256k
- * : CFG_MALLOC_LEN, 128k
+ * : CFG_ENV_SECT_SIZE, 256k
+ * : CFG_MALLOC_LEN, 128k
* 0x00FC 0000 RAM Copy of Monitor Code
- * : CFG_MONITOR_LEN, 256k
+ * : CFG_MONITOR_LEN, 256k
* 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
*/
-/*
+/*
* SBC8260 with 64 MB DIMM:
- *
+ *
* 0x0000 0000 Exception Vector code, 8k
- * :
+ * :
* 0x0000 1FFF
* 0x0000 2000 Free for Application Use
- * :
- * :
+ * :
+ * :
*
- * :
- * :
+ * :
+ * :
* 0x03F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
+ * Monitor Stack Buffer (0x80)
* 0x03F5 FFB0 Board Info Data
* 0x03F6 0000 Malloc Arena
- * : CFG_ENV_SECT_SIZE, 256k
- * : CFG_MALLOC_LEN, 128k
+ * : CFG_ENV_SECT_SIZE, 256k
+ * : CFG_MALLOC_LEN, 128k
* 0x03FC 0000 RAM Copy of Monitor Code
- * : CFG_MONITOR_LEN, 256k
+ * : CFG_MONITOR_LEN, 256k
* 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
*/
#define CONFIG_ETHER_USE_FCC2
#ifdef CONFIG_ETHER_USE_SCC1
-#define CONFIG_ETHER_ON_SCC 1 /* define if ethernet on SCC */
-#undef CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
+#define CONFIG_ETHER_ON_SCC 1 /* define if ethernet on SCC */
+#undef CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
#endif /* CONFIG_ETHER_USE_SCC1 */
#ifdef CONFIG_ETHER_USE_FCC2
-#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
+#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
+#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
/*
* Port pins used for bit-banged MII communictions (if applicable).
*/
-#define MDIO_PORT 2 /* Port C */
+#define MDIO_PORT 2 /* Port C */
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
+ else iop->pdat &= ~0x00400000
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
+ else iop->pdat &= ~0x00200000
#define MIIDELAY udelay(1)
#endif /* CONFIG_ETHER_USE_FCC2 */
/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#if 0
/* Be selective on what keys can delay or stop the autoboot process
* To stop use: " "
*/
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS 0
+# define CONFIG_AUTOBOOT_KEYED
+# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
+# define CONFIG_AUTOBOOT_STOP_STR " "
+# undef CONFIG_AUTOBOOT_DELAY_STR
+# define DEBUG_BOOTKEYS 0
+#endif
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
/* What ppcboot subsytems do you want enabled? */
#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_BEDBUG | \
CFG_CMD_ELF | \
CFG_CMD_ASKENV | \
CFG_CMD_ECHO | \
CFG_CMD_I2C | \
- CFG_CMD_REGINFO | \
+ CFG_CMD_REGINFO | \
CFG_CMD_IMMAP | \
CFG_CMD_MII)
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS 8 /* max number of command args */
+#define CFG_MAXARGS 32 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x140000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
- /* the exception vector table */
+#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
+ /* the exception vector table */
/* to the end of the DRAM */
/* less monitor and malloc area */
#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
/* no slaves */
#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
# define CFG_RAMBOOT
#endif
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
#ifndef CFG_RAMBOOT
# define CFG_ENV_IS_IN_FLASH 1
# ifdef CFG_ENV_IN_OWN_SECT
-# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
-# define CFG_ENV_SECT_SIZE 0x40000
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+# define CFG_ENV_SECT_SIZE 0x40000
# else
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
+# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
# endif /* CFG_ENV_IN_OWN_SECT */
#else
-# define CFG_ENV_IS_IN_NVRAM 1
-# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
-# define CFG_ENV_SIZE 0x200
+# define CFG_ENV_IS_IN_NVRAM 1
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
/*-----------------------------------------------------------------------
* - *CS is output at the same time as the address lines
* - Uses a clock cycle length of 5
* - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
+ * unless *GTA is asserted earlier externally.
* - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
+ * initiated to this memory region.
* - One idle clock is inserted between a read access from the
- * current bank and the next access.
+ * current bank and the next access.
*/
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
ORxG_CSNT |\
*/
/* Bank 2,3 - SDRAM DIMM
- *
- * 16MB DIMM: P/N
+ *
+ * 16MB DIMM: P/N
* 64MB DIMM: P/N 1W-8864X8-4-P1-EST
*
* Note: *CS3 is unused for this DIMM
* - Back-to-back page mode
* - Internal bank interleaving within save device enabled
*/
-#if (CFG_SDRAM0_SIZE == 16)
+#if (CFG_SDRAM0_SIZE == 16)
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
ORxS_BPD_2 |\
ORxS_ROWST_PBI0_A9 |\
* - Back-to-back page mode
* - Internal bank interleaving within save device enabled
*/
-#if (CFG_SDRAM0_SIZE == 64)
+#if (CFG_SDRAM0_SIZE == 64)
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A8 |\
#endif
/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
+ * PSDMR - 60x Bus SDRAM Mode Register
* Ref: Section 10.3.3 on page 10-21
*-----------------------------------------------------------------------
*/
-#if (CFG_SDRAM0_SIZE == 16)
+#if (CFG_SDRAM0_SIZE == 16)
/* With a 16 MB DIMM, the PSDMR is configured as follows:
*
- * - Page Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A16-A18 as bank select,
+ * - Page Based Interleaving,
+ * - Refresh Enable,
+ * - Address Multiplexing where A5 is output on A14 pin
+ * (A6 on A15, and so on),
+ * - use address pins A16-A18 as bank select,
* - A9 is output on SDA10 during an ACTIVATE command,
* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
+ * is 3 clocks,
+ * - earliest timing for READ/WRITE command after ACTIVATE command is
+ * 2 clocks,
+ * - earliest timing for PRECHARGE after last data was read is 1 clock,
+ * - earliest timing for PRECHARGE after last data was written is 1 clock,
* - CAS Latency is 2.
*/
#define CFG_PSDMR (PSDMR_RFEN |\
PSDMR_CL_2)
#endif
-#if (CFG_SDRAM0_SIZE == 64)
+#if (CFG_SDRAM0_SIZE == 64)
/* With a 64 MB DIMM, the PSDMR is configured as follows:
*
- * - Page Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A14-A16 as bank select,
+ * - Page Based Interleaving,
+ * - Refresh Enable,
+ * - Address Multiplexing where A5 is output on A14 pin
+ * (A6 on A15, and so on),
+ * - use address pins A14-A16 as bank select,
* - A9 is output on SDA10 during an ACTIVATE command,
* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
+ * is 3 clocks,
+ * - earliest timing for READ/WRITE command after ACTIVATE command is
+ * 2 clocks,
+ * - earliest timing for PRECHARGE after last data was read is 1 clock,
+ * - earliest timing for PRECHARGE after last data was written is 1 clock,
* - CAS Latency is 2.
*/
#define CFG_PSDMR (PSDMR_RFEN |\
* - *CS is output at the same time as the address lines
* - Uses a clock cycle length of 5
* - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
+ * unless *GTA is asserted earlier externally.
* - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
+ * initiated to this memory region.
* - One idle clock is inserted between a read access from the
- * current bank and the next access.
+ * current bank and the next access.
*/
# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
ORxG_CSNT |\
* - *CS is output at the same time as the address lines
* - Uses a clock cycle length of 15
* - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
+ * unless *GTA is asserted earlier externally.
* - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
+ * initiated to this memory region.
* - One idle clock is inserted between a read access from the
- * current bank and the next access.
+ * current bank and the next access.
*/
# define CFG_OR7_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
projects / users / rw / ppcboot.git / commitdiff