struct radeon_bo                *robj;
        struct ttm_validate_buffer      tv;
        uint64_t                        gpu_offset;
-       unsigned                        prefered_domains;
+       unsigned                        preferred_domains;
        unsigned                        allowed_domains;
        uint32_t                        tiling_flags;
 };
 
                     p->rdev->family == CHIP_RS880)) {
 
                        /* TODO: is this still needed for NI+ ? */
-                       p->relocs[i].prefered_domains =
+                       p->relocs[i].preferred_domains =
                                RADEON_GEM_DOMAIN_VRAM;
 
                        p->relocs[i].allowed_domains =
                                return -EINVAL;
                        }
 
-                       p->relocs[i].prefered_domains = domain;
+                       p->relocs[i].preferred_domains = domain;
                        if (domain == RADEON_GEM_DOMAIN_VRAM)
                                domain |= RADEON_GEM_DOMAIN_GTT;
                        p->relocs[i].allowed_domains = domain;
                }
 
                if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
-                       uint32_t domain = p->relocs[i].prefered_domains;
+                       uint32_t domain = p->relocs[i].preferred_domains;
                        if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
                                DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
                                          "allowed for userptr BOs\n");
                        }
                        need_mmap_lock = true;
                        domain = RADEON_GEM_DOMAIN_GTT;
-                       p->relocs[i].prefered_domains = domain;
+                       p->relocs[i].preferred_domains = domain;
                        p->relocs[i].allowed_domains = domain;
                }
 
 
        list_for_each_entry(lobj, head, tv.head) {
                struct radeon_bo *bo = lobj->robj;
                if (!bo->pin_count) {
-                       u32 domain = lobj->prefered_domains;
+                       u32 domain = lobj->preferred_domains;
                        u32 allowed = lobj->allowed_domains;
                        u32 current_domain =
                                radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 
 
        /* add the vm page table to the list */
        list[0].robj = vm->page_directory;
-       list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
+       list[0].preferred_domains = RADEON_GEM_DOMAIN_VRAM;
        list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
        list[0].tv.bo = &vm->page_directory->tbo;
        list[0].tv.shared = true;
                        continue;
 
                list[idx].robj = vm->page_tables[i].bo;
-               list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
+               list[idx].preferred_domains = RADEON_GEM_DOMAIN_VRAM;
                list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
                list[idx].tv.bo = &list[idx].robj->tbo;
                list[idx].tv.shared = true;