amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
                amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
                amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+               if (is_support_sw_smu(adev))
+                       amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
                if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                        amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
                amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 
 
 include $(AMD_POWERPLAY)
 
-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o
+POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o
 
 AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
 
 
 #include "amdgpu_smu.h"
 #include "soc15_common.h"
 #include "smu_v11_0.h"
+#include "smu_v12_0.h"
 #include "atom.h"
 #include "amd_pcie.h"
 
                        smu->od_enabled = true;
                smu_v11_0_set_smu_funcs(smu);
                break;
+       case CHIP_RENOIR:
+               adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+               if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+                       smu->od_enabled = true;
+               smu_v12_0_set_smu_funcs(smu);
+               break;
        default:
                return -EINVAL;
        }
        struct amdgpu_device *adev = smu->adev;
        int ret;
 
+       if (adev->flags & AMD_IS_APU)
+               return 0;
+
        if (smu_is_dpm_running(smu) && adev->in_suspend) {
                pr_info("dpm has been enabled\n");
                return 0;
        .rev = 0,
        .funcs = &smu_ip_funcs,
 };
+
+const struct amdgpu_ip_block_version smu_v12_0_ip_block =
+{
+       .type = AMD_IP_BLOCK_TYPE_SMC,
+       .major = 12,
+       .minor = 0,
+       .rev = 0,
+       .funcs = &smu_ip_funcs,
+};
 
 extern const struct amd_ip_funcs smu_ip_funcs;
 
 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
+extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
+
 extern int smu_feature_init_dpm(struct smu_context *smu);
 
 extern int smu_feature_is_enabled(struct smu_context *smu,