octeontx2-af: configure default CPT credits for CN10KA B0

The maximum CPT credits that RXC can use are now configurable on CN10KA B0
through a hardware CSR. This patch sets the default value to optimize peak
performance, aligning it with other chip versions.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 64c9c9ee000d65408055243c045f9fd8e4e3c1c6..43b1d83686d1641d1a6e9affa0629b38c1802140 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -691,6 +691,26 @@ static inline bool is_cnf10ka_a0(struct rvu *rvu)
        return false;
 }
 
+static inline bool is_cn10ka_a0(struct rvu *rvu)
+{
+       struct pci_dev *pdev = rvu->pdev;
+
+       if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
+           (pdev->revision & 0x0F) == 0x0)
+               return true;
+       return false;
+}
+
+static inline bool is_cn10ka_a1(struct rvu *rvu)
+{
+       struct pci_dev *pdev = rvu->pdev;
+
+       if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
+           (pdev->revision & 0x0F) == 0x1)
+               return true;
+       return false;
+}
+
 static inline bool is_cn10kb(struct rvu *rvu)
 {
        struct pci_dev *pdev = rvu->pdev;

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index d44614a63a7bba934c26de7633946ed50764f1f8..3c5bbaf12e594c7d96a2e1584f519b197a18a8e7 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -22,6 +22,9 @@
 /* Interrupt vector count of CPT RVU and RAS interrupts */
 #define CPT_10K_AF_RVU_RAS_INT_VEC_CNT  2
 
+/* Default CPT_AF_RXC_CFG1:max_rxc_icb_cnt */
+#define CPT_DFLT_MAX_RXC_ICB_CNT  0xC0ULL
+
 #define cpt_get_eng_sts(e_min, e_max, rsp, etype)                   \
 ({                                                                  \
        u64 free_sts = 0, busy_sts = 0;                             \
@@ -737,6 +740,7 @@ static bool validate_and_update_reg_offset(struct rvu *rvu,
                case CPT_AF_BLK_RST:
                case CPT_AF_CONSTANTS1:
                case CPT_AF_CTX_FLUSH_TIMER:
+               case CPT_AF_RXC_CFG1:
                        return true;
                }
 
@@ -1285,9 +1289,12 @@ unlock:
        return 0;
 }
 
+#define MAX_RXC_ICB_CNT  GENMASK_ULL(40, 32)
+
 int rvu_cpt_init(struct rvu *rvu)
 {
        struct rvu_hwinfo *hw = rvu->hw;
+       u64 reg_val;
 
        /* Retrieve CPT PF number */
        rvu->cpt_pf_num = get_cpt_pf_num(rvu);
@@ -1295,6 +1302,17 @@ int rvu_cpt_init(struct rvu *rvu)
            !is_cn10kb(rvu))
                hw->cap.cpt_rxc = true;
 
+       if (hw->cap.cpt_rxc && !is_cn10ka_a0(rvu) && !is_cn10ka_a1(rvu)) {
+               /* Set CPT_AF_RXC_CFG1:max_rxc_icb_cnt to 0xc0 to not effect
+                * inline inbound peak performance
+                */
+               reg_val = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_RXC_CFG1);
+               reg_val &= ~MAX_RXC_ICB_CNT;
+               reg_val |= FIELD_PREP(MAX_RXC_ICB_CNT,
+                                     CPT_DFLT_MAX_RXC_ICB_CNT);
+               rvu_write64(rvu, BLKADDR_CPT0, CPT_AF_RXC_CFG1, reg_val);
+       }
+
        spin_lock_init(&rvu->cpt_intr_lock);
 
        return 0;

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
index d56be5fb7eb4a2fafd7c0bc7feca6f2a742e8ab6..2b299fa85159137fc3c708aa95719ed349eb44b7 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
@@ -545,6 +545,7 @@
 #define CPT_AF_CTX_PSH_PC               (0x49450ull)
 #define CPT_AF_CTX_PSH_LATENCY_PC       (0x49458ull)
 #define CPT_AF_CTX_CAM_DATA(a)          (0x49800ull | (u64)(a) << 3)
+#define CPT_AF_RXC_CFG1                 (0x50000ull)
 #define CPT_AF_RXC_TIME                 (0x50010ull)
 #define CPT_AF_RXC_TIME_CFG             (0x50018ull)
 #define CPT_AF_RXC_DFRG                 (0x50020ull)