Modifications for 1.2.0:
======================================================================
+* Patch by Greg Allen, 6 Aug 2002:
+ Support for UTX8245 Board
+
* Patch by Scott McNutt / Jun Gu / Stefan Roese, 05 Aug 2002:
Support for IBM 440GP Ebony Board (and 440 in general)
GEN860T MPC860T
+Greg Allen <gallen@arlut.utexas.edu>
+
+ UTX8245 MPC8245
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
LIST_824x=" \
CU824 MOUSSE MUSENKI OXC \
Sandpoint8240 Sandpoint8245 \
+ utx8245 \
"
#########################################################################
Sandpoint8245_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x sandpoint
+utx8245_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc824x utx8245
#########################################################################
## MPC8260 Systems
Files specific to Walnut405 boards
- board/westel/ Files specific to boards manufactured by Westel Wireless
- board/westel/amx860 Files specific to AMX860 boards
-
+- board/utx8245 Files specific to UTX8245 boards
Software Configuration:
=======================
CONFIG_GENIETV, CONFIG_PM826, CONFIG_ppmc8260,
CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto,
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
- CONFIG_ICU862
+ CONFIG_ICU862 CONFIG_UTX8245
- CPU Module Type: (if CONFIG_COGENT is defined)
Define exactly one of
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
+#if 0
static void flash_get_offsets (ulong base, flash_info_t *info);
+#endif
#ifdef CONFIG_ADCIOP
#define ADDR0 0x0aa9
/*-----------------------------------------------------------------------
*/
+#if 0
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
}
}
}
+#endif /* 0 */
/*-----------------------------------------------------------------------
*/
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-/*************************************************************************/
-/* TLB TABLE
+/**************************************************************************
+ * TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
*
* Pointer to the table is returned in r1
*
-/*************************************************************************/
+ *************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Gregory E. Allen, gallen@arlut.utexas.edu
+# Matthew E. Karger, karger@arlut.utexas.edu
+# Applied Research Laboratories, The University of Texas at Austin
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+SOBJS =
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Gregory E. Allen, gallen@arlut.utexas.edu
+# Matthew E. Karger, karger@arlut.utexas.edu
+# Applied Research Laboratories, The University of Texas at Austin
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# UTX8245 boards
+#
+TEXT_BASE = 0xFFF00000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#define ROM_CS0_START 0xFF800000
+#define ROM_CS1_START 0xFF000000
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x200000
+#define MAIN_SECT_SIZE 0x10000
+#define SECT_SIZE_32KB 0x8000
+#define SECT_SIZE_8KB 0x2000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+static __inline__ unsigned long get_msr(void)
+{ unsigned long msr;
+ __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+ return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+ __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
+
+/*flash command address offsets*/
+#define ADDR0 (0x555)
+#define ADDR1 (0xAAA)
+#define ADDR3 (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*---------------------------------------------------------------------*/
+//#define DEBUG_FLASH 1
+
+/*---------------------------------------------------------------------*/
+
+unsigned long flash_init(void)
+{
+ int i, j;
+ ulong size = 0;
+ unsigned char manuf_id, device_id;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ {
+ vu_char *addr = (vu_char *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+ addr[0x555] = 0xAA; // 3 cycles to read device info. See
+ addr[0x2AA] = 0x55; // AM29LV116D datasheet for list of
+ addr[0x555] = 0x90; // available commands.
+
+ manuf_id = addr[0];
+ device_id = addr[1];
+
+#if defined DEBUG_FLASH
+ printf("manuf_id = %x, device_id = %x\n", manuf_id, device_id);
+#endif
+
+ if ( (manuf_id == (uchar)(AMD_MANUFACT)) &&
+ ( device_id == AMD_ID_LV116DT))
+ {
+ flash_info[i].flash_id = ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
+ (AMD_ID_LV116DT & FLASH_TYPEMASK);
+ } else {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ addr[0] = (long)0xFFFFFFFF;
+ goto Done;
+ }
+
+#if defined DEBUG_FLASH
+ printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+#endif
+
+ addr[0] = (long)0xFFFFFFFF;
+
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+ for (j = 0; j < flash_info[i].sector_count; j++)
+ {
+
+ if (j < (CFG_MAX_FLASH_SECT - 3) )
+
+ flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+ j * MAIN_SECT_SIZE;
+
+ else if (j == (CFG_MAX_FLASH_SECT - 3) )
+
+ flash_info[i].start[j] = flash_info[i].start[j-1] + SECT_SIZE_32KB;
+
+
+ else
+
+ flash_info[i].start[j] = flash_info[i].start[j-1] + SECT_SIZE_8KB;
+
+ }
+
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+ flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+Done:
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+ static const char unk[] = "Unknown";
+ const char *mfct = unk, *type = unk;
+ unsigned int i;
+
+ if(info->flash_id != FLASH_UNKNOWN)
+ {
+ switch(info->flash_id & FLASH_VENDMASK)
+ {
+ case FLASH_MAN_AMD: mfct = "AMD"; break;
+ case FLASH_MAN_FUJ: mfct = "FUJITSU"; break;
+ case FLASH_MAN_STM: mfct = "STM"; break;
+ case FLASH_MAN_SST: mfct = "SST"; break;
+ case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break;
+ case FLASH_MAN_INTEL: mfct = "Intel"; break;
+ }
+
+ switch(info->flash_id & FLASH_TYPEMASK)
+ {
+ case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break;
+ case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break;
+ case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break;
+ case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break;
+ case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break;
+ case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break;
+ case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break;
+ case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break;
+ case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break;
+ case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break;
+ case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break;
+ }
+ }
+
+ printf(
+ "\n Brand: %s Type: %s\n"
+ " Size: %lu KB in %d Sectors\n",
+ mfct,
+ type,
+ info->size >> 10,
+ info->sector_count
+ );
+
+ printf (" Sector Start Addresses:");
+
+ for (i = 0; i < info->sector_count; i++)
+ {
+ unsigned long size;
+ unsigned int erased;
+ unsigned long * flash = (unsigned long *) info->start[i];
+
+ /*
+ * Check if whole sector is erased
+ */
+ size =
+ (i != (info->sector_count - 1)) ?
+ (info->start[i + 1] - info->start[i]) >> 2 :
+ (info->start[0] + info->size - info->start[i]) >> 2;
+
+ for(
+ flash = (unsigned long *) info->start[i], erased = 1;
+ (flash != (unsigned long *) info->start[i] + size) && erased;
+ flash++
+ )
+ erased = *flash == ~0x0UL;
+
+ printf(
+ "%s %08lX %s %s",
+ (i % 5) ? "" : "\n ",
+ info->start[i],
+ erased ? "E" : " ",
+ info->protect[i] ? "RO" : " "
+ );
+ }
+
+ puts("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ unsigned char sh8b;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Check the ROM CS */
+ if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
+ sh8b = 3;
+ else
+ sh8b = 0;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++)
+ {
+ if (info->protect[sect] == 0)
+ { /* not protected */
+ addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+ (info->start[sect] - info->start[0]) << sh8b));
+
+ if (info->flash_id & FLASH_MAN_SST)
+ {
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
+ udelay(30000); /* wait 30 ms */
+ }
+
+ else
+ addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+ (info->start[l_sect] - info->start[0]) << sh8b));
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ volatile FLASH_WORD_SIZE *dest2;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ ulong start;
+ int flag;
+ int i;
+ unsigned char sh8b;
+
+ /* Check the ROM CS */
+ if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
+ sh8b = 3;
+ else
+ sh8b = 0;
+
+ dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
+ info->start[0]);
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+ {
+ addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i << sh8b] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc824x/start.o (.text)
+ common/board.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define SAVE_SZ 32
+
+
+ /* We have to clear the initial data area here. Couldn't have done it
+ * earlier because DRAM had not been initialized.
+ */
+int board_pre_init(void)
+{
+ memset((void *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET),
+ 0, CFG_INIT_DATA_SIZE);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ ulong busfreq = get_bus_freq(0);
+ char buf[32];
+
+ printf("UTX8245 ");
+ printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+
+ return 0;
+}
+
+
+long int initdram(int board_type)
+{
+#if 1
+ int i, cnt;
+ volatile uchar *base = CFG_SDRAM_BASE;
+ volatile ulong *addr;
+ ulong save[SAVE_SZ];
+ ulong val, ret = 0;
+
+ for (i=0; i<SAVE_SZ; i++) {save[i] = 0;} /* clear table */
+
+ for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1)
+ {
+ addr = (volatile ulong *)base + cnt;
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ addr = (volatile ulong *)base;
+ save[i] = *addr;
+ *addr = 0;
+
+ if (*addr != 0)
+ {
+ *addr = save[i];
+ goto Done;
+ }
+
+ for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1)
+ {
+ addr = (volatile ulong *)base + cnt;
+ val = *addr;
+ *addr = save[--i];
+ if (val != ~cnt)
+ {
+ ulong new_bank0_end = cnt * sizeof(long) - 1;
+ ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
+ ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ ret = cnt * sizeof(long);
+ goto Done;
+ }
+ }
+
+ ret = CFG_MAX_RAM_SIZE;
+Done:
+ return ret;
+#else
+ return (CFG_MAX_RAM_SIZE);
+#endif
+
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+static struct pci_config_table pci_utx8245_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
+ PCI_FIREWIRE_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
+ { }
+};
+
+
+static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ if (PCI_DEV(dev) == 11)
+ /* assign serial interrupt line 9 (int25) to FireWire */
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
+
+ else if (PCI_DEV(dev) == 12)
+ /* assign serial interrupt line 8 (int24) to Ethernet */
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
+}
+
+static struct pci_controller utx8245_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_utx8245_config_table,
+ fixup_irq: pci_utx8245_fixup_irq,
+ write_byte: pci_hose_write_config_byte
+#endif /*CONFIG_PCI_PNP*/
+};
+
+void pci_init (bd_t *bd)
+{
+ pci_mpc824x_init(bd, &utx8245_hose);
+
+ icache_enable();
+}
+
#include <asm/processor.h>
#include <mpc824x.h>
+#ifndef CFG_BANK0_ROW
+#define CFG_BANK0_ROW 0
+#endif
+#ifndef CFG_BANK1_ROW
+#define CFG_BANK1_ROW 0
+#endif
+#ifndef CFG_BANK2_ROW
+#define CFG_BANK2_ROW 0
+#endif
+#ifndef CFG_BANK3_ROW
+#define CFG_BANK3_ROW 0
+#endif
+#ifndef CFG_BANK4_ROW
+#define CFG_BANK4_ROW 0
+#endif
+#ifndef CFG_BANK5_ROW
+#define CFG_BANK5_ROW 0
+#endif
+#ifndef CFG_BANK6_ROW
+#define CFG_BANK6_ROW 0
+#endif
+#ifndef CFG_BANK7_ROW
+#define CFG_BANK7_ROW 0
+#endif
+#ifndef CFG_DBUS_SIZE2
+#define CFG_DBUS_SIZE2 0
+#endif
+
/*
* Breath some life into the CPU...
*
PICR1_PROC_TYPE_603E |
PICR1_FLASH_WR_EN | PICR1_MCP_EN |
PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
- PICR1_DEC| PICR1_CF_APARK );
+ PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
#ifndef CFG_RAMBOOT
CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
+ (CFG_BANK0_ROW) |
+ (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
+ (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
+ (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
+ (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
+ (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
+ (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
+ (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
(CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif
(CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+ (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
(((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
(val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
(CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
+#ifdef CFG_DLL_MAX_DELAY
+ CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */
+#endif
+#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL)
+ CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL);
+#endif
+#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD)
+ CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */
+#endif /* setup & hold time */
+
CONFIG_WRITE_BYTE(MBER,
CFG_BANK0_ENABLE |
(CFG_BANK1_ENABLE << 1) |
int checkcpu(long clock)
{
uint pvr = get_pvr();
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_IOP480)
char buf[32];
+#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
PPC405_SYS_INFO sys_info;
void serial_init (ulong cpu_clock, int baudrate)
{
unsigned long reg;
- unsigned long tmp;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ unsigned long tmp;
+#endif
reg = mfdcr(cntrl0) & ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#undef CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
+#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE \
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the utx8245 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8245 1
+#define CONFIG_UTX8245 1
+#define DEBUG 1
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 57600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_BOOTCOMMAND "bootm FF920000 FF800000" /* autoboot command */
+#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
+#define CONFIG_ETHADDR 41:52:4c:61:00:01 /* MAC address */
+#define CONFIG_SERVERIP 10.8.17.105
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
+ | CFG_CMD_FLASH | CFG_CMD_MEMORY \
+ | CFG_CMD_ENV | CFG_CMD_CONSOLE \
+ | CFG_CMD_LOADS | CFG_CMD_LOADB \
+ | CFG_CMD_IMI | CFG_CMD_CACHE \
+ | CFG_CMD_RUN | CFG_CMD_ECHO \
+ | CFG_CMD_REGINFO | CFG_CMD_NET\
+ | CFG_CMD_DHCP)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
+
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+
+#define PCI_ENET0_IOADDR 0x80000000
+#define PCI_ENET0_MEMADDR 0x80000000
+#define PCI_FIREWIRE_IOADDR 0x81000000
+#define PCI_FIREWIRE_MEMADDR 0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE 0x10000000 /* amount of SDRAM */
+
+
+/* even though FLASHP_BASE is FF800000, with 2MB on RCS0, the
+ * reset vector is actually located at FF800100, but the 8245
+ * takes care of us.
+ */
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_EUMB_ADDR 0xFC000000
+
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*#define CFG_DRAM_TEST 1 */
+#define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
+#define CFG_MEMTEST_END 0x0ff8ffa8 /* in SDRAM, skips exception */
+ /* vectors and PPCBoot */
+
+
+/*--------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ *------------------------------------------------------------------*/
+#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
+ /* initial data */
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+
+/*--------------------------------------------------------------------
+ * NS16550 Configuration
+ *------------------------------------------------------------------*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE 1
+
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
+
+/*--------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ *------------------------------------------------------------------*/
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define CFG_HZ 1000
+
+#define CFG_ETH_DEV_FN 0x7800
+#define CFG_ETH_IOBASE 0x00104000
+
+
+/*--------------------------------------------------------------------
+ * Memory Control Configuration Register values
+ * - see sec. 4.12 of MPC8245 UM
+ *------------------------------------------------------------------*/
+
+// MCCR1
+#define CFG_ROMNAL 0
+#define CFG_ROMFAL 2 /* (tacc=70ns)*mem_freq - 2 */
+#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
+#define CFG_BANK1_ROW 2 /* bit count */
+#define CFG_BANK2_ROW 0
+#define CFG_BANK3_ROW 0
+#define CFG_BANK4_ROW 0
+#define CFG_BANK5_ROW 0
+#define CFG_BANK6_ROW 0
+#define CFG_BANK7_ROW 0
+
+/* MCCR2, refresh interval clock cycles */
+#define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4 */
+#define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */
+ /* sets open page interval */
+
+/* MCCR3 */
+#define CFG_REFREC 5 /* Refresh to activate interval, trc */
+
+/* MCCR4 */
+#define CFG_PRETOACT 2 /* trp */
+#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + tdrl */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
+#define CFG_ACTORW 2 /* trcd min */
+#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+/* calculate according to formula in sec. 6-22 of 8245 UM */
+#define CFG_PGMAX 50 /* how long the 8245 retains the */
+ /* currently accessed page in memory */
+ /* was 45 */
+
+#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
+ /* bottom 3 bits MUST be 0 */
+
+#define CFG_DLL_MAX_DELAY 0x04
+#define CFG_DLL_EXTEND 0x80
+#define CFG_PCI_HOLD_DEL 0x20
+
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these values to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8245 user manual.
+ */
+
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2
+#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK1_ENABLE 1
+#define CFG_BANK2_START 0x3ff00000 /* not available in this design */
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x3ff00000
+#define CFG_BANK4_END 0x3fffffff
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x3ff00000
+#define CFG_BANK5_END 0x3fffffff
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x3ff00000
+#define CFG_BANK6_END 0x3fffffff
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x3ff00000
+#define CFG_BANK7_END 0x3fffffff
+#define CFG_BANK7_ENABLE 0
+
+/*--------------------------------------------------------------------
+ * 4.4 - Output Driver Control Register
+ *------------------------------------------------------------------*/
+#define CFG_ODCR 0xe5
+
+/*--------------------------------------------------------------------
+ * 4.8 - Error Handling Registers
+ *------------------------------------------------------------------*/
+#define CFG_ERRENR1 0x11 // enable SDRAM refresh overflow error
+
+/* SDRAM 0-256 MB */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in dcache */
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory */
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc. */
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization (AMD AM29LV116D)
+ */
+#define CFG_FLASH_BASE 0xFF800000
+
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+ /* Warning: environment is not EMBEDDED in the ppcboot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+
+#define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
+#define CFG_ENV_SIZE 0x2000 /* Size of the Environment */
+#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
+#define CFG_ENV_SECT_SIZE 0x2000 /* Size of the Environment Sector */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+#endif /* __CONFIG_H */
#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
+#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
#define FLASH_AM400B 0x0003
#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
#define FLASH_AM800B 0x0005
+#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
#define FLASH_AM160B 0x0007
#define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */
#define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */
#define ERRENR1 0x800000c0 /* Error Enableing Register 1 */
-#define ERRENR2 0x800000c0 /* Error Enableing Register 2 */
+#define ERRENR2 0x800000c4 /* Error Enableing Register 2 */
#define ERRDR1 0x800000c1 /* Error Detection Register 1 */
#define IPBESR 0x800000c3 /* Internal Processor Error Status Register */
#define ERRDR2 0x800000c5 /* Error Detection Register 2 */
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define MCCR1_PCKEN 0x00010000
+#define MCCR1_BANK1ROW_SHIFT 2
+#define MCCR1_BANK2ROW_SHIFT 4
+#define MCCR1_BANK3ROW_SHIFT 6
+#define MCCR1_BANK4ROW_SHIFT 8
+#define MCCR1_BANK5ROW_SHIFT 10
+#define MCCR1_BANK6ROW_SHIFT 12
+#define MCCR1_BANK7ROW_SHIFT 14
#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
#define MCCR2_TS_WAIT_TIMER_SHIFT 29
projects / users / rw / ppcboot.git / commitdiff