cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport

Same as for ports, also store the downstream port's Component Register
mappings, use struct cxl_dport for that.

Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-16-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 43ffecebf1d8c7e75b6168eaf2f305f717ebbe17..cbd3d17f6410d649b1fa72128294c57f9972c55a 100644 (file)
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -711,6 +711,13 @@ static inline int cxl_port_setup_regs(struct cxl_port *port,
                                   component_reg_phys);
 }
 
+static inline int cxl_dport_setup_regs(struct cxl_dport *dport,
+                                      resource_size_t component_reg_phys)
+{
+       return cxl_setup_comp_regs(dport->dport_dev, &dport->comp_map,
+                                  component_reg_phys);
+}
+
 static struct cxl_port *__devm_cxl_add_port(struct device *host,
                                            struct device *uport_dev,
                                            resource_size_t component_reg_phys,
@@ -989,6 +996,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
        dport->port_id = port_id;
        dport->port = port;
 
+       rc = cxl_dport_setup_regs(dport, component_reg_phys);
+       if (rc)
+               return ERR_PTR(rc);
+
        cond_cxl_root_lock(port);
        rc = add_dport(port, dport);
        cond_cxl_root_unlock(port);

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 37fa5b565362aa88e5ea6bc2c337a322b655ef57..b1adca9b27ba56b3cc70980664648b8f39784e66 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -595,6 +595,7 @@ struct cxl_rcrb_info {
 /**
  * struct cxl_dport - CXL downstream port
  * @dport_dev: PCI bridge or firmware device representing the downstream link
+ * @comp_map: component register capability mappings
  * @port_id: unique hardware identifier for dport in decoder target list
  * @rcrb: Data about the Root Complex Register Block layout
  * @rch: Indicate whether this dport was enumerated in RCH or VH mode
@@ -602,6 +603,7 @@ struct cxl_rcrb_info {
  */
 struct cxl_dport {
        struct device *dport_dev;
+       struct cxl_register_map comp_map;
        int port_id;
        struct cxl_rcrb_info rcrb;
        bool rch;