CXL_HDM_DECODER0_CTRL_HOSTONLY);
 }
 
-static int cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt)
+static void cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt)
 {
        struct cxl_dport **t = &cxlsd->target[0];
        int ways = cxlsd->cxld.interleave_ways;
 
-       if (dev_WARN_ONCE(&cxlsd->cxld.dev,
-                         ways > 8 || ways > cxlsd->nr_targets,
-                         "ways: %d overflows targets: %d\n", ways,
-                         cxlsd->nr_targets))
-               return -ENXIO;
-
        *tgt = FIELD_PREP(GENMASK(7, 0), t[0]->port_id);
        if (ways > 1)
                *tgt |= FIELD_PREP(GENMASK(15, 8), t[1]->port_id);
                *tgt |= FIELD_PREP(GENMASK_ULL(55, 48), t[6]->port_id);
        if (ways > 7)
                *tgt |= FIELD_PREP(GENMASK_ULL(63, 56), t[7]->port_id);
-
-       return 0;
 }
 
 /*
                void __iomem *tl_lo = hdm + CXL_HDM_DECODER0_TL_LOW(id);
                u64 targets;
 
-               rc = cxlsd_set_targets(cxlsd, &targets);
-               if (rc) {
-                       dev_dbg(&port->dev, "%s: target configuration error\n",
-                               dev_name(&cxld->dev));
-                       goto err;
-               }
-
+               cxlsd_set_targets(cxlsd, &targets);
                writel(upper_32_bits(targets), tl_hi);
                writel(lower_32_bits(targets), tl_lo);
        } else {
 
        port->commit_end++;
        rc = cxld_await_commit(hdm, cxld->id);
-err:
        if (rc) {
                dev_dbg(&port->dev, "%s: error %d committing decoder\n",
                        dev_name(&cxld->dev), rc);
 
                return rc;
        }
 
+       if (iw > 8 || iw > cxlsd->nr_targets) {
+               dev_dbg(&cxlr->dev,
+                       "%s:%s:%s: ways: %d overflows targets: %d\n",
+                       dev_name(port->uport_dev), dev_name(&port->dev),
+                       dev_name(&cxld->dev), iw, cxlsd->nr_targets);
+               return -ENXIO;
+       }
+
        if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
                if (cxld->interleave_ways != iw ||
                    cxld->interleave_granularity != ig ||