arm64: dts: qcom: sm8650: add OPP table support to PCIe

The PCIe bus interconnect path can be scaled depending on the
PCIe link established, add the OPP table with all the possible
link speeds and the associated power domain level.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-8-eaa8b10e2af7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index ded6afd220a563a30a4e750cecaadd7a238b4b3c..e6938d04c40bae97d52e150eae0240b0e1654c67 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3241,6 +3241,8 @@
 
                        power-domains = <&gcc PCIE_0_GDSC>;
 
+                       operating-points-v2 = <&pcie0_opp_table>;
+
                        iommu-map = <0     &apps_smmu 0x1400 0x1>,
                                    <0x100 &apps_smmu 0x1401 0x1>;
 
@@ -3271,6 +3273,45 @@
 
                        status = "disabled";
 
+                       pcie0_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               /* GEN 1 x1 */
+                               opp-2500000 {
+                                       opp-hz = /bits/ 64 <2500000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <250000 1>;
+                               };
+
+                               /* GEN 1 x2 and GEN 2 x1 */
+                               opp-5000000 {
+                                       opp-hz = /bits/ 64 <5000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <500000 1>;
+                               };
+
+                               /* GEN 2 x2 */
+                               opp-10000000 {
+                                       opp-hz = /bits/ 64 <10000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <1000000 1>;
+                               };
+
+                               /* GEN 3 x1 */
+                               opp-8000000 {
+                                       opp-hz = /bits/ 64 <8000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <984500 1>;
+                               };
+
+                               /* GEN 3 x2 */
+                               opp-16000000 {
+                                       opp-hz = /bits/ 64 <16000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <1969000 1>;
+                               };
+                       };
+
                        pcieport0: pcie@0 {
                                device_type = "pci";
                                reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -3380,6 +3421,8 @@
 
                        power-domains = <&gcc PCIE_1_GDSC>;
 
+                       operating-points-v2 = <&pcie1_opp_table>;
+
                        iommu-map = <0     &apps_smmu 0x1480 0x1>,
                                    <0x100 &apps_smmu 0x1481 0x1>;
 
@@ -3410,6 +3453,52 @@
 
                        status = "disabled";
 
+                       pcie1_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               /* GEN 1 x1 */
+                               opp-2500000 {
+                                       opp-hz = /bits/ 64 <2500000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <250000 1>;
+                               };
+
+                               /* GEN 1 x2 and GEN 2 x1 */
+                               opp-5000000 {
+                                       opp-hz = /bits/ 64 <5000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <500000 1>;
+                               };
+
+                               /* GEN 2 x2 */
+                               opp-10000000 {
+                                       opp-hz = /bits/ 64 <10000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <1000000 1>;
+                               };
+
+                               /* GEN 3 x1 */
+                               opp-8000000 {
+                                       opp-hz = /bits/ 64 <8000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <984500 1>;
+                               };
+
+                               /* GEN 3 x2 and GEN 4 x1 */
+                               opp-16000000 {
+                                       opp-hz = /bits/ 64 <16000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <1969000 1>;
+                               };
+
+                               /* GEN 4 x2 */
+                               opp-32000000 {
+                                       opp-hz = /bits/ 64 <32000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <3938000 1>;
+                               };
+                       };
+
                        pcie@0 {
                                device_type = "pci";
                                reg = <0x0 0x0 0x0 0x0 0x0>;