net: dsa: lan9303: ensure chip reset and wait for READY status

Accessing device registers seems to be not reliable, the chip
revision is sometimes detected wrongly (0 instead of expected 1).

Ensure that the chip reset is performed via reset GPIO and then
wait for 'Device Ready' status in HW_CFG register before doing
any register initializations.

Cc: stable@vger.kernel.org
Fixes: a1292595e006 ("net: dsa: add new DSA switch driver for the SMSC-LAN9303")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
[alex: reworked using read_poll_timeout()]
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://patch.msgid.link/20241004113655.3436296-1-alexander.sverdlin@siemens.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/dsa/lan9303-core.c b/drivers/net/dsa/lan9303-core.c
index 268949939636a0e406554647fef0854129142e8d..d246f95d57ecf8ef648e9cfa259fca1d174b033c 100644 (file)
--- a/drivers/net/dsa/lan9303-core.c
+++ b/drivers/net/dsa/lan9303-core.c
@@ -6,6 +6,7 @@
 #include <linux/module.h>
 #include <linux/gpio/consumer.h>
 #include <linux/regmap.h>
+#include <linux/iopoll.h>
 #include <linux/mutex.h>
 #include <linux/mii.h>
 #include <linux/of.h>
@@ -839,6 +840,8 @@ static void lan9303_handle_reset(struct lan9303 *chip)
        if (!chip->reset_gpio)
                return;
 
+       gpiod_set_value_cansleep(chip->reset_gpio, 1);
+
        if (chip->reset_duration != 0)
                msleep(chip->reset_duration);
 
@@ -864,8 +867,34 @@ static int lan9303_disable_processing(struct lan9303 *chip)
 static int lan9303_check_device(struct lan9303 *chip)
 {
        int ret;
+       int err;
        u32 reg;
 
+       /* In I2C-managed configurations this polling loop will clash with
+        * switch's reading of EEPROM right after reset and this behaviour is
+        * not configurable. While lan9303_read() already has quite long retry
+        * timeout, seems not all cases are being detected as arbitration error.
+        *
+        * According to datasheet, EEPROM loader has 30ms timeout (in case of
+        * missing EEPROM).
+        *
+        * Loading of the largest supported EEPROM is expected to take at least
+        * 5.9s.
+        */
+       err = read_poll_timeout(lan9303_read, ret,
+                               !ret && reg & LAN9303_HW_CFG_READY,
+                               20000, 6000000, false,
+                               chip->regmap, LAN9303_HW_CFG, &reg);
+       if (ret) {
+               dev_err(chip->dev, "failed to read HW_CFG reg: %pe\n",
+                       ERR_PTR(ret));
+               return ret;
+       }
+       if (err) {
+               dev_err(chip->dev, "HW_CFG not ready: 0x%08x\n", reg);
+               return err;
+       }
+
        ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, &reg);
        if (ret) {
                dev_err(chip->dev, "failed to read chip revision register: %d\n",