int max_lane_count;
/* Max rate for the current link */
int max_rate;
+ /* Sequential link training failures after a passing LT */
+ int seq_train_failures;
} link;
bool reset_link_params;
int mso_link_count;
{
intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
+ intel_dp->link.seq_train_failures = 0;
}
/* Enable backlight PWM and backlight PP control. */
intel_dp->lane_count))
return false;
+ if (intel_dp->link.seq_train_failures)
+ return true;
+
/* Retrain if link not ok */
return !intel_dp_link_ok(intel_dp, link_status);
}
passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
if (passed) {
+ intel_dp->link.seq_train_failures = 0;
intel_encoder_link_check_queue_work(encoder, 2000);
return;
}
+ intel_dp->link.seq_train_failures++;
+
/*
* Ignore the link failure in CI
*
return;
}
+ if (intel_dp->link.seq_train_failures < 2) {
+ intel_encoder_link_check_queue_work(encoder, 0);
+ return;
+ }
+
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
}