Merge branch 'pci/controller/imx6'

- Add DT compatible string 'fsl,imx8q-pcie-ep' and driver support for
  i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) Endpoints (Frank Li)

- Add DT binding for optional i.MX95 Refclk and driver support to enable it
  if the platform hasn't enabled it (Richard Zhu)

- Configure PHY based on controller being in Root Complex or Endpoint mode
  (Frank Li)

- Rely on dbi2 and iATU base addresses from DT via dw_pcie_get_resources()
  instead of hardcoding them in imx6 (Richard Zhu)

- Skip controller_id computation for i.MX7D since it only has one
  controller (Richard Zhu)

- Deassert apps_reset in imx_pcie_deassert_core_reset() since it is
  asserted in imx_pcie_assert_core_reset() (Richard Zhu)

- Add missing reference clock enable or disable logic for IMX6SX, IMX7D,
  IMX8MM (Richard Zhu)

- Remove redundant imx7d_pcie_init_phy() since imx7d_pcie_enable_ref_clk()
  does the same thing (Richard Zhu)

* pci/controller/imx6:
  PCI: imx6: Clean up comments and whitespace
  PCI: imx6: Remove surplus imx7d_pcie_init_phy() function
  PCI: imx6: Add missing reference clock disable logic
  PCI: imx6: Deassert apps_reset in imx_pcie_deassert_core_reset()
  PCI: imx6: Skip controller_id generation logic for i.MX7D
  PCI: imx6: Fetch dbi2 and iATU base addesses from DT
  PCI: imx6: Configure PHY based on Root Complex or Endpoint mode
  PCI: imx6: Add Refclk for i.MX95 PCIe
  dt-bindings: PCI: fsl,imx6q-pcie: Add Refclk for i.MX95 RC
  PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
  dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep

# Conflicts:
#	drivers/pci/controller/dwc/pci-imx6.c

diff --cc drivers/pci/controller/dwc/pci-imx6.c
index 9734399aefde45b11834bbc6caa73109921d1b45,d70e6c4279766974955a00a4aba98f35a74954ad..90ace941090f90d8b95abe5c979a794638b88255
--- 1/drivers/pci/controller/dwc/pci-imx6.c
--- 2/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@@ -1808,11 -1617,10 +1798,12 @@@ static const struct imx_pcie_drvdata dr
        },
        [IMX95] = {
                .variant = IMX95,
 -              .flags = IMX_PCIE_FLAG_HAS_SERDES,
 +              .flags = IMX_PCIE_FLAG_HAS_SERDES |
 +                       IMX_PCIE_FLAG_HAS_LUT |
 +                       IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
-               .clk_names = imx8mq_clks,
-               .clks_cnt = ARRAY_SIZE(imx8mq_clks),
+               .clk_names = imx95_clks,
+               .clks_cnt = ARRAY_SIZE(imx95_clks),
+               .clks_optional_cnt = 1,
                .ltssm_off = IMX95_PE0_GEN_CTRL_3,
                .ltssm_mask = IMX95_PCIE_LTSSM_EN,
                .mode_off[0]  = IMX95_PE0_GEN_CTRL_1,