phy: qcom-qmp: pcs-ufs: Add v6 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
new file mode 100644 (file)
index 0000000..c23d5e4
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
+#define QCOM_PHY_QMP_PCS_UFS_V6_H_
+
+/* Only for QMP V6 PHY - UFS PCS registers */
+#define QPHY_V6_PCS_UFS_PHY_START                      0x000
+#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL             0x004
+#define QPHY_V6_PCS_UFS_SW_RESET                       0x008
+#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB   0x00c
+#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB   0x010
+#define QPHY_V6_PCS_UFS_PLL_CNTL                       0x02c
+#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL           0x030
+#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL           0x038
+#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL            0x060
+#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY           0x074
+#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY           0x0bc
+#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL               0x158
+#define QPHY_V6_PCS_UFS_LINECFG_DISABLE                        0x17c
+#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME            0x184
+#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2                        0x18c
+#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND               0x178
+#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND                        0x174
+#define QPHY_V6_PCS_UFS_READY_STATUS                   0x1a8
+#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1              0x1f4
+#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1               0x1fc
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 12ce7138f8efe03f755f60d99e78f8a974830d7c..f0b007844ccaea706f22e373457910f7f9a76100 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -26,6 +26,7 @@
 #include "phy-qcom-qmp-pcs-ufs-v3.h"
 #include "phy-qcom-qmp-pcs-ufs-v4.h"
 #include "phy-qcom-qmp-pcs-ufs-v5.h"
+#include "phy-qcom-qmp-pcs-ufs-v6.h"
 
 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"