arm64/sysreg: Standardise naming for CTR_EL0 fields

cache.h contains some defines which are used to represent fields and
enumeration values which do not follow the standard naming convention used for
when we automatically generate defines for system registers. Update the
names of the constants to reflect standardised naming and move them to
sysreg.h.

There is also a helper CTR_L1IP() which was open coded and has been
converted to use SYS_FIELD_GET().

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-7-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index da4886b1922bfce2983a57f3334950dd3a91a548..ca9b487112ccbfa6c1c2d55dea2a781004356bdc 100644 (file)
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -5,24 +5,6 @@
 #ifndef __ASM_CACHE_H
 #define __ASM_CACHE_H
 
-#define CTR_L1IP_SHIFT         14
-#define CTR_L1IP_MASK          3
-#define CTR_DMINLINE_SHIFT     16
-#define CTR_IMINLINE_SHIFT     0
-#define CTR_IMINLINE_MASK      0xf
-#define CTR_ERG_SHIFT          20
-#define CTR_CWG_SHIFT          24
-#define CTR_CWG_MASK           15
-#define CTR_IDC_SHIFT          28
-#define CTR_DIC_SHIFT          29
-
-#define CTR_CACHE_MINLINE_MASK \
-       (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
-
-#define ICACHE_POLICY_VPIPT    0
-#define ICACHE_POLICY_VIPT     2
-#define ICACHE_POLICY_PIPT     3
-
 #define L1_CACHE_SHIFT         (6)
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
@@ -50,6 +32,7 @@
 
 #include <asm/cputype.h>
 #include <asm/mte-def.h>
+#include <asm/sysreg.h>
 
 #ifdef CONFIG_KASAN_SW_TAGS
 #define ARCH_SLAB_MINALIGN     (1ULL << KASAN_SHADOW_SCALE_SHIFT)
@@ -62,7 +45,11 @@ static inline unsigned int arch_slab_minalign(void)
 #define arch_slab_minalign() arch_slab_minalign()
 #endif
 
-#define CTR_L1IP(ctr)          (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
+#define CTR_CACHE_MINLINE_MASK \
+       (0xf << CTR_EL0_DMINLINE_SHIFT | \
+        CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)
+
+#define CTR_L1IP(ctr)          SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
 
 #define ICACHEF_ALIASING       0
 #define ICACHEF_VPIPT          1
@@ -84,7 +71,7 @@ static __always_inline int icache_is_vpipt(void)
 
 static inline u32 cache_type_cwg(void)
 {
-       return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
+       return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;
 }
 
 #define __read_mostly __section(".data..read_mostly")
@@ -118,12 +105,12 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
 {
        u32 ctr = read_cpuid_cachetype();
 
-       if (!(ctr & BIT(CTR_IDC_SHIFT))) {
+       if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
                u64 clidr = read_sysreg(clidr_el1);
 
                if (CLIDR_LOC(clidr) == 0 ||
                    (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
-                       ctr |= BIT(CTR_IDC_SHIFT);
+                       ctr |= BIT(CTR_EL0_IDC_SHIFT);
        }
 
        return ctr;

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 58286c83d592d4b41d00cf4365642be010fede4b..c4293754954ef589fa796cb41f2b2f868d1a5526 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1084,6 +1084,21 @@
 #define MVFR2_FPMISC_SHIFT             4
 #define MVFR2_SIMDMISC_SHIFT           0
 
+#define CTR_EL0_L1Ip_VPIPT             0
+#define CTR_EL0_L1Ip_VIPT              2
+#define CTR_EL0_L1Ip_PIPT              3
+
+#define CTR_EL0_L1Ip_SHIFT             14
+#define CTR_EL0_L1Ip_MASK              3
+#define CTR_EL0_DminLine_SHIFT         16
+#define CTR_EL0_IminLine_SHIFT         0
+#define CTR_EL0_IminLine_MASK          0xf
+#define CTR_EL0_ERG_SHIFT              20
+#define CTR_EL0_CWG_SHIFT              24
+#define CTR_EL0_CWG_MASK               15
+#define CTR_EL0_IDC_SHIFT              28
+#define CTR_EL0_DIC_SHIFT              29
+
 #define DCZID_DZP_SHIFT                        4
 #define DCZID_BS_SHIFT                 0
 

diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
index 7bbf5104b7b7bd9985849a774051abb591d07b0d..9bcaa5eacf16cf1ccf76d64f1886f52c54caef77 100644 (file)
--- a/arch/arm64/kernel/alternative.c
+++ b/arch/arm64/kernel/alternative.c
@@ -121,7 +121,7 @@ static void clean_dcache_range_nopatch(u64 start, u64 end)
 
        ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
        d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
-                                                          CTR_DMINLINE_SHIFT);
+                                                          CTR_EL0_DminLine_SHIFT);
        cur = start & ~(d_size - 1);
        do {
                /*

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index c05cc3b6162e921a3cc28d42adc14dcf4f33650e..a0dd3ea8f585b9f3a477045acecac5e8653a88e9 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -187,7 +187,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
                                int scope)
 {
        u32 midr = read_cpuid_id();
-       bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
+       bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
        const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
 
        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8d88433de81da0a0ecf890f8328433fa4a0c4d9a..b7cd50eb6d8a1c205283794b36d5cc599b08ba57 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -396,18 +396,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 
 static const struct arm64_ftr_bits ftr_ctr[] = {
        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
        /*
         * Linux can handle differing I-cache policies. Userspace JITs will
         * make use of *minLine.
         * If we have differing I-cache policies, report it as the weakest - VIPT.
         */
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT),   /* L1Ip */
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT),        /* L1Ip */
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -1480,7 +1480,7 @@ static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
        else
                ctr = read_cpuid_effective_cachetype();
 
-       return ctr & BIT(CTR_IDC_SHIFT);
+       return ctr & BIT(CTR_EL0_IDC_SHIFT);
 }
 
 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
@@ -1491,7 +1491,7 @@ static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unu
         * to the CTR_EL0 on this CPU and emulate it with the real/safe
         * value.
         */
-       if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
+       if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
                sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 }
 
@@ -1505,7 +1505,7 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
        else
                ctr = read_cpuid_cachetype();
 
-       return ctr & BIT(CTR_DIC_SHIFT);
+       return ctr & BIT(CTR_EL0_DIC_SHIFT);
 }
 
 static bool __maybe_unused

diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index deaaa9438fc2064d1052daab3e21ca72afe3d9f8..e1e72789982122e9c5dbc8b3877a02ba2a32c1af 100644 (file)
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -36,11 +36,11 @@ static struct cpuinfo_arm64 boot_cpu_data;
 static inline const char *icache_policy_str(int l1ip)
 {
        switch (l1ip) {
-       case ICACHE_POLICY_VPIPT:
+       case CTR_EL0_L1Ip_VPIPT:
                return "VPIPT";
-       case ICACHE_POLICY_VIPT:
+       case CTR_EL0_L1Ip_VIPT:
                return "VIPT";
-       case ICACHE_POLICY_PIPT:
+       case CTR_EL0_L1Ip_PIPT:
                return "PIPT";
        default:
                return "RESERVED/UNKNOWN";
@@ -349,12 +349,12 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
        u32 l1ip = CTR_L1IP(info->reg_ctr);
 
        switch (l1ip) {
-       case ICACHE_POLICY_PIPT:
+       case CTR_EL0_L1Ip_PIPT:
                break;
-       case ICACHE_POLICY_VPIPT:
+       case CTR_EL0_L1Ip_VPIPT:
                set_bit(ICACHEF_VPIPT, &__icache_flags);
                break;
-       case ICACHE_POLICY_VIPT:
+       case CTR_EL0_L1Ip_VIPT:
        default:
                /* Assume aliasing */
                set_bit(ICACHEF_ALIASING, &__icache_flags);

diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 9ac7a81b79be853e6344f8a565bd3be9bcc10c2c..b7fed33981f7b7683900f7e7f961d67fed6c51bc 100644 (file)
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -579,11 +579,11 @@ static void ctr_read_handler(unsigned long esr, struct pt_regs *regs)
 
        if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
                /* Hide DIC so that we can trap the unnecessary maintenance...*/
-               val &= ~BIT(CTR_DIC_SHIFT);
+               val &= ~BIT(CTR_EL0_DIC_SHIFT);
 
                /* ... and fake IminLine to reduce the number of traps. */
-               val &= ~CTR_IMINLINE_MASK;
-               val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
+               val &= ~CTR_EL0_IminLine_MASK;
+               val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK;
        }
 
        pt_regs_write_reg(regs, rt, val);