if (CAN_PANEL_REPLAY(intel_dp))
                crtc_state->has_panel_replay = true;
-       else
-               crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
 
-       if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
+       crtc_state->has_psr = crtc_state->has_panel_replay ? true :
+               _psr_compute_config(intel_dp, crtc_state);
+
+       if (!crtc_state->has_psr)
                return;
 
        crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
                goto unlock;
 
        if (intel_dp->psr.panel_replay_enabled) {
-               pipe_config->has_panel_replay = true;
+               pipe_config->has_psr = pipe_config->has_panel_replay = true;
        } else {
                /*
                 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
                intel_atomic_get_new_crtc_state(state, crtc);
        struct intel_encoder *encoder;
 
-       if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
+       if (!crtc_state->has_psr)
                return;
 
        for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,