powerpc/32: move MSR_PR test into EXCEPTION_PROLOG_0

In order to simplify  VMAP stack implementation, move
MSR_PR test into EXCEPTION_PROLOG_0.

This requires to not modify cr0 between EXCEPTION_PROLOG_0
and EXCEPTION_PROLOG_1.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/5c8b5bba692b92654dbd363a229a1ba91db725bb.1576916812.git.christophe.leroy@c-s.fr

diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
index 8e345f8d4b0e1535a38e1e1a6dce6fd6a9a1e52c..436ffd862d2a308738ba88f095a50679d9e68765 100644 (file)
--- a/arch/powerpc/kernel/head_32.h
+++ b/arch/powerpc/kernel/head_32.h
@@ -19,12 +19,12 @@
 .macro EXCEPTION_PROLOG_0
        mtspr   SPRN_SPRG_SCRATCH0,r10
        mtspr   SPRN_SPRG_SCRATCH1,r11
+       mfspr   r11, SPRN_SRR1          /* check whether user or kernel */
        mfcr    r10
+       andi.   r11, r11, MSR_PR
 .endm
 
 .macro EXCEPTION_PROLOG_1
-       mfspr   r11,SPRN_SRR1           /* check whether user or kernel */
-       andi.   r11,r11,MSR_PR
        tophys(r11,r1)                  /* use tophys(r1) if kernel */
        beq     1f
        mfspr   r11,SPRN_SPRG_THREAD

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index fb284d95c76abe72e668a9859dccdc7b539a64bc..175c3cfc8014f08908d01ac14020dc4d27201b3f 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -497,8 +497,8 @@ InstructionTLBError:
 DataTLBError:
        EXCEPTION_PROLOG_0
        mfspr   r11, SPRN_DAR
-       cmpwi   cr0, r11, RPN_PATTERN
-       beq-    FixupDAR        /* must be a buggy dcbX, icbi insn. */
+       cmpwi   cr1, r11, RPN_PATTERN
+       beq-    cr1, FixupDAR   /* must be a buggy dcbX, icbi insn. */
 DARFixed:/* Return from dcbx instruction bug workaround */
        EXCEPTION_PROLOG_1
        EXCEPTION_PROLOG_2
@@ -531,9 +531,9 @@ DARFixed:/* Return from dcbx instruction bug workaround */
 DataBreakpoint:
        EXCEPTION_PROLOG_0
        mfspr   r11, SPRN_SRR0
-       cmplwi  cr0, r11, (.Ldtlbie - PAGE_OFFSET)@l
+       cmplwi  cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
        cmplwi  cr7, r11, (.Litlbie - PAGE_OFFSET)@l
-       beq-    cr0, 11f
+       beq-    cr1, 11f
        beq-    cr7, 11f
        EXCEPTION_PROLOG_1
        EXCEPTION_PROLOG_2
@@ -578,9 +578,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
        mfspr   r10, SPRN_SRR0
        mtspr   SPRN_MD_EPN, r10
        rlwinm  r11, r10, 16, 0xfff8
-       cmpli   cr0, r11, PAGE_OFFSET@h
+       cmpli   cr1, r11, PAGE_OFFSET@h
        mfspr   r11, SPRN_M_TWB /* Get level 1 table */
-       blt+    3f
+       blt+    cr1, 3f
        rlwinm  r11, r10, 16, 0xfff8
 
 0:     cmpli   cr7, r11, (PAGE_OFFSET + 0x1800000)@h
@@ -595,7 +595,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
 3:
        lwz     r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)        /* Get the level 1 entry */
        mtspr   SPRN_MD_TWC, r11
-       mtcr    r11
+       mtcrf   0x01, r11
        mfspr   r11, SPRN_MD_TWC
        lwz     r11, 0(r11)     /* Get the pte */
        bt      28,200f         /* bit 28 = Large page (8M) */
@@ -608,16 +608,16 @@ FixupDAR:/* Entry point for dcbx workaround. */
  * no need to include them here */
        xoris   r10, r11, 0x7c00        /* check if major OP code is 31 */
        rlwinm  r10, r10, 0, 21, 5
-       cmpwi   cr0, r10, 2028  /* Is dcbz? */
-       beq+    142f
-       cmpwi   cr0, r10, 940   /* Is dcbi? */
-       beq+    142f
-       cmpwi   cr0, r10, 108   /* Is dcbst? */
-       beq+    144f            /* Fix up store bit! */
-       cmpwi   cr0, r10, 172   /* Is dcbf? */
-       beq+    142f
-       cmpwi   cr0, r10, 1964  /* Is icbi? */
-       beq+    142f
+       cmpwi   cr1, r10, 2028  /* Is dcbz? */
+       beq+    cr1, 142f
+       cmpwi   cr1, r10, 940   /* Is dcbi? */
+       beq+    cr1, 142f
+       cmpwi   cr1, r10, 108   /* Is dcbst? */
+       beq+    cr1, 144f               /* Fix up store bit! */
+       cmpwi   cr1, r10, 172   /* Is dcbf? */
+       beq+    cr1, 142f
+       cmpwi   cr1, r10, 1964  /* Is icbi? */
+       beq+    cr1, 142f
 141:   mfspr   r10,SPRN_M_TW
        b       DARFixed        /* Nope, go back to normal TLB processing */
 
@@ -676,8 +676,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
        add     r10, r10, r30   ;b      151f
        add     r10, r10, r31
 151:
-       rlwinm. r11,r11,19,24,28        /* offset into jump table for reg RA */
-       beq     152f                    /* if reg RA is zero, don't add it */
+       rlwinm  r11,r11,19,24,28        /* offset into jump table for reg RA */
+       cmpwi   cr1, r11, 0
+       beq     cr1, 152f               /* if reg RA is zero, don't add it */
        addi    r11, r11, 150b@l        /* add start of table */
        mtctr   r11                     /* load ctr with jump address */
        rlwinm  r11,r11,0,16,10         /* make sure we don't execute this more than once */