.hipc = &cnl_hipc_spec,
 };
 
+#define AVS_TGL_BASED_SPEC(sname)              \
+static const struct avs_spec sname##_desc = {  \
+       .name = #sname,                         \
+       .min_fw_version = { 10, 29, 0, 5646 },  \
+       .dsp_ops = &avs_tgl_dsp_ops,            \
+       .core_init_mask = 1,                    \
+       .attributes = AVS_PLATATTR_IMR,         \
+       .sram = &apl_sram_spec,                 \
+       .hipc = &cnl_hipc_spec,                 \
+}
+
+AVS_TGL_BASED_SPEC(lkf);
+AVS_TGL_BASED_SPEC(tgl);
+AVS_TGL_BASED_SPEC(ehl);
+AVS_TGL_BASED_SPEC(adl);
+AVS_TGL_BASED_SPEC(adl_n);
+
 static const struct pci_device_id avs_ids[] = {
        { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, &skl_desc) },
        { PCI_DEVICE_DATA(INTEL, HDA_SKL, &skl_desc) },
        { PCI_DEVICE_DATA(INTEL, HDA_ICL_N,     &icl_desc) },
        { PCI_DEVICE_DATA(INTEL, HDA_ICL_H,     &icl_desc) },
        { PCI_DEVICE_DATA(INTEL, HDA_JSL_N,     &jsl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_LKF,       &lkf_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP,    &tgl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_TGL_H,     &tgl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_CML_R,     &tgl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_EHL_0,     &ehl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_EHL_3,     &ehl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_ADL_S,     &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_ADL_P,     &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS,    &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_ADL_M,     &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX,    &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_ADL_N,     &adl_n_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_RPL_S,     &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0,   &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1,   &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_RPL_M,     &adl_desc) },
+       { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX,    &adl_desc) },
        { 0 }
 };
 MODULE_DEVICE_TABLE(pci, avs_ids);
 
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright(c) 2021-2024 Intel Corporation. All rights reserved.
+//
+// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
+//          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
+//
+
+#include "avs.h"
+
+static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
+{
+       core_mask &= AVS_MAIN_CORE_MASK;
+
+       if (!core_mask)
+               return 0;
+       return avs_dsp_core_power(adev, core_mask, power);
+}
+
+static int avs_tgl_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
+{
+       core_mask &= AVS_MAIN_CORE_MASK;
+
+       if (!core_mask)
+               return 0;
+       return avs_dsp_core_reset(adev, core_mask, reset);
+}
+
+static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
+{
+       core_mask &= AVS_MAIN_CORE_MASK;
+
+       if (!core_mask)
+               return 0;
+       return avs_dsp_core_stall(adev, core_mask, stall);
+}
+
+const struct avs_dsp_ops avs_tgl_dsp_ops = {
+       .power = avs_tgl_dsp_core_power,
+       .reset = avs_tgl_dsp_core_reset,
+       .stall = avs_tgl_dsp_core_stall,
+       .irq_handler = avs_irq_handler,
+       .irq_thread = avs_cnl_irq_thread,
+       .int_control = avs_dsp_interrupt_control,
+       .load_basefw = avs_hda_load_basefw,
+       .load_lib = avs_hda_load_library,
+       .transfer_mods = avs_hda_transfer_modules,
+       .log_buffer_offset = avs_icl_log_buffer_offset,
+       .log_buffer_status = avs_apl_log_buffer_status,
+       .coredump = avs_apl_coredump,
+       .d0ix_toggle = avs_icl_d0ix_toggle,
+       .set_d0ix = avs_icl_set_d0ix,
+       AVS_SET_ENABLE_LOGS_OP(icl)
+};