RISC-V: Re-enable counter access from userspace

These counters were part of the ISA when we froze the uABI, removing
them breaks userspace.

Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/
Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220928131807.30386-1-palmer@rivosinc.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 15e5a47be7d59c44c02ea0583fd3978d404d142f..3852c18362f53ec2630a7f10c5a6d6e6baf59a9c 100644 (file)
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -652,8 +652,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
        struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
        struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
 
-       /* Enable the access for TIME csr only from the user mode now */
-       csr_write(CSR_SCOUNTEREN, 0x2);
+       /*
+        * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,
+        * as is necessary to maintain uABI compatibility.
+        */
+       csr_write(CSR_SCOUNTEREN, 0x7);
 
        /* Stop all the counters so that they can be enabled from perf */
        pmu_sbi_stop_all(pmu);