u32 mask2 = 0;
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        struct ath_common *common = ath9k_hw_common(ah);
-       struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
        u32 sync_cause = 0, async_cause;
 
        async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
                        ar9003_hw_bb_watchdog_read(ah);
        }
 
-       if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
-               u32 raw_intr, rx_msg_intr;
-
-               rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
-               raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
-
-               if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
-                       ath_dbg(common, MCI,
-                               "MCI gets 0xdeadbeef during MCI int processing new raw_intr=0x%08x, new rx_msg_raw=0x%08x, raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
-                               raw_intr, rx_msg_intr, mci->raw_intr,
-                               mci->rx_msg_intr);
-               else {
-                       mci->rx_msg_intr |= rx_msg_intr;
-                       mci->raw_intr |= raw_intr;
-                       *masked |= ATH9K_INT_MCI;
-
-                       if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
-                               mci->cont_status =
-                                       REG_READ(ah, AR_MCI_CONT_STATUS);
-
-                       REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
-                       REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
-                       ath_dbg(common, MCI, "AR_INTR_SYNC_MCI\n");
-
-               }
-       }
+       if (async_cause & AR_INTR_ASYNC_MASK_MCI)
+               ar9003_mci_get_isr(ah, masked);
 
        if (sync_cause) {
                if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
 
 }
 EXPORT_SYMBOL(ar9003_mci_get_interrupt);
 
+void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
+{
+       struct ath_common *common = ath9k_hw_common(ah);
+       struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+       u32 raw_intr, rx_msg_intr;
+
+       rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
+       raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
+
+       if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) {
+               ath_dbg(common, MCI,
+                       "MCI gets 0xdeadbeef during int processing\n");
+       } else {
+               mci->rx_msg_intr |= rx_msg_intr;
+               mci->raw_intr |= raw_intr;
+               *masked |= ATH9K_INT_MCI;
+
+               if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
+                       mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS);
+
+               REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
+               REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
+       }
+}
+
 void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
 {
        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 
 void ar9003_mci_sync_bt_state(struct ath_hw *ah);
 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
                              u32 *rx_msg_intr);
+void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
 
 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 static inline enum ath_btcoex_scheme