{
        struct drm_i915_private *i915 = uncore_to_i915(uncore);
 
-       if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
+       if (!intel_uncore_has_forcewake(uncore))
                return;
 
        if (INTEL_GEN(i915) >= 11) {
 
        i915_check_vgpu(i915);
 
+       if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
+               uncore->flags |= UNCORE_HAS_FORCEWAKE;
+
        intel_uncore_edram_detect(i915);
        intel_uncore_fw_domains_init(uncore);
        __intel_uncore_early_sanitize(uncore, 0);
        uncore->pmic_bus_access_nb.notifier_call =
                i915_pmic_bus_access_notifier;
 
-       if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
-               ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
-               ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
-       } else if (IS_GEN(i915, 5)) {
-               ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
-               ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+       if (!intel_uncore_has_forcewake(uncore)) {
+               if (IS_GEN(i915, 5)) {
+                       ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
+                       ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+               } else {
+                       ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
+                       ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
+               }
        } else if (IS_GEN_RANGE(i915, 6, 7)) {
                ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
 
        } else if (INTEL_GEN(dev_priv) >= 6) {
                fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
        } else {
-               WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
+               /* on devices with FW we expect to hit one of the above cases */
+               if (intel_uncore_has_forcewake(uncore))
+                       MISSING_CASE(INTEL_GEN(dev_priv));
+
                fw_domains = 0;
        }
 
        } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
                fw_domains = FORCEWAKE_RENDER;
        } else {
-               WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
+               /* on devices with FW we expect to hit one of the above cases */
+               if (intel_uncore_has_forcewake(uncore))
+                       MISSING_CASE(INTEL_GEN(dev_priv));
+
                fw_domains = 0;
        }
 
 
        WARN_ON(!op);
 
-       if (intel_vgpu_active(dev_priv))
+       if (!intel_uncore_has_forcewake(&dev_priv->uncore))
                return 0;
 
        if (op & FW_REG_READ)
 
 
        spinlock_t lock; /** lock is also taken in irq contexts. */
 
+       unsigned int flags;
+#define UNCORE_HAS_FORCEWAKE           BIT(0)
+
        const struct intel_forcewake_range *fw_domains_table;
        unsigned int fw_domains_table_entries;
 
        return container_of(d, struct intel_uncore, fw_domain[d->id]);
 }
 
+static inline bool
+intel_uncore_has_forcewake(const struct intel_uncore *uncore)
+{
+       return uncore->flags & UNCORE_HAS_FORCEWAKE;
+}
+
 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
 int intel_uncore_init(struct intel_uncore *uncore);
 void intel_uncore_prune(struct intel_uncore *uncore);