drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update

We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.

It shouldn't be necessary to have SFF bit set if CFF bit is set in
PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not
reason to have it different on older platforms.

v2: commit message improved

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-2-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 861e50ceef8596e42210f043a199f0985cb37e5f..64e03d19cad5da63b32ab4340fc096cd32373789 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2395,7 +2395,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
        val |= man_trk_ctl_partial_frame_bit_get(display);
 
        if (full_update) {
-               val |= man_trk_ctl_single_full_frame_bit_get(display);
                val |= man_trk_ctl_continuos_full_frame(display);
                goto exit;
        }