struct s3c24xx_uart_info {
        char                    *name;
        enum s3c24xx_port_type  type;
-       bool                    has_usi;
        unsigned int            port_type;
        unsigned int            fifosize;
        unsigned long           rx_fifomask;
        return ret;
 }
 
-static void exynos_usi_init(struct uart_port *port)
-{
-       struct s3c24xx_uart_port *ourport = to_ourport(port);
-       struct s3c24xx_uart_info *info = ourport->info;
-       unsigned int val;
-
-       if (!info->has_usi)
-               return;
-
-       /* Clear the software reset of USI block (it's set at startup) */
-       val = rd_regl(port, USI_CON);
-       val &= ~USI_CON_RESET_MASK;
-       wr_regl(port, USI_CON, val);
-       udelay(1);
-
-       /* Continuously provide the clock to USI IP w/o gating (for Rx mode) */
-       val = rd_regl(port, USI_OPTION);
-       val &= ~USI_OPTION_HWACG_MASK;
-       val |= USI_OPTION_HWACG_CLKREQ_ON;
-       wr_regl(port, USI_OPTION, val);
-}
-
 /* power power management control */
 
 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
 
                if (!IS_ERR(ourport->baudclk))
                        clk_prepare_enable(ourport->baudclk);
-
-               exynos_usi_init(port);
                break;
        default:
                dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
        if (ret)
                pr_warn("uart: failed to enable baudclk\n");
 
-       exynos_usi_init(port);
-
        /* Keep all interrupts masked and cleared */
        switch (ourport->info->type) {
        case TYPE_S3C6400:
 #endif
 
 #if defined(CONFIG_ARCH_EXYNOS)
-#define EXYNOS_COMMON_SERIAL_DRV_DATA(_has_usi)                        \
+#define EXYNOS_COMMON_SERIAL_DRV_DATA()                                \
        .info = &(struct s3c24xx_uart_info) {                   \
                .name           = "Samsung Exynos UART",        \
                .type           = TYPE_S3C6400,                 \
-               .has_usi        = _has_usi,                     \
                .port_type      = PORT_S3C6400,                 \
                .has_divslot    = 1,                            \
                .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
        }                                                       \
 
 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
-       EXYNOS_COMMON_SERIAL_DRV_DATA(false),
+       EXYNOS_COMMON_SERIAL_DRV_DATA(),
        .fifosize = { 256, 64, 16, 16 },
 };
 
 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
-       EXYNOS_COMMON_SERIAL_DRV_DATA(false),
+       EXYNOS_COMMON_SERIAL_DRV_DATA(),
        .fifosize = { 64, 256, 16, 256 },
 };
 
 static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
-       EXYNOS_COMMON_SERIAL_DRV_DATA(true),
+       EXYNOS_COMMON_SERIAL_DRV_DATA(),
        .fifosize = { 256, 64, 64, 64 },
 };