return 0;
 }
 
+static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
+                                    struct phylink_config *config)
+{
+       switch (port) {
+       case 0 ... 4: /* Internal phy */
+               __set_bit(PHY_INTERFACE_MODE_GMII,
+                         config->supported_interfaces);
+               break;
+
+       case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
+               phy_interface_set_rgmii(config->supported_interfaces);
+               __set_bit(PHY_INTERFACE_MODE_MII,
+                         config->supported_interfaces);
+               __set_bit(PHY_INTERFACE_MODE_GMII,
+                         config->supported_interfaces);
+               break;
+
+       case 6: /* 1st cpu port */
+               __set_bit(PHY_INTERFACE_MODE_RGMII,
+                         config->supported_interfaces);
+               __set_bit(PHY_INTERFACE_MODE_TRGMII,
+                         config->supported_interfaces);
+               break;
+       }
+}
+
 static bool
 mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
                          const struct phylink_link_state *state)
        return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
 }
 
+static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
+                                    struct phylink_config *config)
+{
+       struct mt7530_priv *priv = ds->priv;
+
+       switch (port) {
+       case 0 ... 4: /* Internal phy */
+               __set_bit(PHY_INTERFACE_MODE_GMII,
+                         config->supported_interfaces);
+               break;
+
+       case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
+               if (mt7531_is_rgmii_port(priv, port)) {
+                       phy_interface_set_rgmii(config->supported_interfaces);
+                       break;
+               }
+               fallthrough;
+
+       case 6: /* 1st cpu port supports sgmii/8023z only */
+               __set_bit(PHY_INTERFACE_MODE_SGMII,
+                         config->supported_interfaces);
+               __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+                         config->supported_interfaces);
+               __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+                         config->supported_interfaces);
+
+               config->mac_capabilities |= MAC_2500FD;
+               break;
+       }
+}
+
 static bool
 mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
                          const struct phylink_link_state *state)
        return 0;
 }
 
+static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+                                   struct phylink_config *config)
+{
+       struct mt7530_priv *priv = ds->priv;
+
+       /* This switch only supports full-duplex at 1Gbps */
+       config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+                                  MAC_10 | MAC_100 | MAC_1000FD;
+
+       priv->info->mac_port_get_caps(ds, port, config);
+}
+
 static void
 mt7530_mac_port_validate(struct dsa_switch *ds, int port,
                         unsigned long *supported)
        .port_vlan_del          = mt7530_port_vlan_del,
        .port_mirror_add        = mt753x_port_mirror_add,
        .port_mirror_del        = mt753x_port_mirror_del,
+       .phylink_get_caps       = mt753x_phylink_get_caps,
        .phylink_validate       = mt753x_phylink_validate,
        .phylink_mac_link_state = mt753x_phylink_mac_link_state,
        .phylink_mac_config     = mt753x_phylink_mac_config,
                .phy_read = mt7530_phy_read,
                .phy_write = mt7530_phy_write,
                .pad_setup = mt7530_pad_clk_setup,
+               .mac_port_get_caps = mt7530_mac_port_get_caps,
                .phy_mode_supported = mt7530_phy_mode_supported,
                .mac_port_validate = mt7530_mac_port_validate,
                .mac_port_get_state = mt7530_phylink_mac_link_state,
                .phy_read = mt7530_phy_read,
                .phy_write = mt7530_phy_write,
                .pad_setup = mt7530_pad_clk_setup,
+               .mac_port_get_caps = mt7530_mac_port_get_caps,
                .phy_mode_supported = mt7530_phy_mode_supported,
                .mac_port_validate = mt7530_mac_port_validate,
                .mac_port_get_state = mt7530_phylink_mac_link_state,
                .phy_write = mt7531_ind_phy_write,
                .pad_setup = mt7531_pad_setup,
                .cpu_port_config = mt7531_cpu_port_config,
+               .mac_port_get_caps = mt7531_mac_port_get_caps,
                .phy_mode_supported = mt7531_phy_mode_supported,
                .mac_port_validate = mt7531_mac_port_validate,
                .mac_port_get_state = mt7531_phylink_mac_link_state,
         */
        if (!priv->info->sw_setup || !priv->info->pad_setup ||
            !priv->info->phy_read || !priv->info->phy_write ||
+           !priv->info->mac_port_get_caps ||
            !priv->info->phy_mode_supported ||
            !priv->info->mac_port_validate ||
            !priv->info->mac_port_get_state || !priv->info->mac_port_config)